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101. 发明授权

US06733953B2 Photomask and pattern forming method employing the same 失效
标题翻译：光掩模和使用其的图案形成方法
公开(公告)号：US06733953B2
公开(公告)日：2004-05-11
申请号：US10096599
申请日：2002-03-14
申请人： Norio Hasegawa , Fumio Murai , Katsuya Hayano
发明人： Norio Hasegawa , Fumio Murai , Katsuya Hayano
IPC分类号： G03C500
CPC分类号： G03F1/32 , G03F1/26 , G03F1/29 , G03F7/2022 , G03F7/70066
摘要： A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.
摘要翻译：半透射相移掩模在图形元件区域的外围具有由半透射相移部分和具有最佳尺寸组合的透明部分形成的遮光部分。使用半透明相移掩模形成图案。

102. 发明授权

US06649956B2 Semiconductor integrated circuit device and manufacturing method thereof 有权
公开(公告)号：US06649956B2
公开(公告)日：2003-11-18
申请号：US10227799
申请日：2002-08-27
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

103. 发明授权

US06538855B1 Magneto-resistive thin film magnetic head preventing entry of unnecessary magnetic flux and having good reproduction characteristics 失效
标题翻译：磁阻薄膜磁头防止不必要的磁通进入并具有良好的再生特性
公开(公告)号：US06538855B1
公开(公告)日：2003-03-25
申请号：US09717668
申请日：2000-11-21
申请人： Akira Nakamura , Morio Kondo , Norio Hasegawa , Yasuhiko Shinjo , Kenji Machida , Naoto Hayashi , Kazutoshi Mutou , Toshihiro Uehara , Junji Numazawa
发明人： Akira Nakamura , Morio Kondo , Norio Hasegawa , Yasuhiko Shinjo , Kenji Machida , Naoto Hayashi , Kazutoshi Mutou , Toshihiro Uehara , Junji Numazawa
IPC分类号： G11B539
CPC分类号： G11B5/3925 , G11B5/11 , G11B5/3146
摘要： A magneto-resistive thin film magnetic head is provided, which magnetic head includes: a base; a first yoke provided on the base and separated by a gap into first and second portions, the first portion including a side which opposes a magnetic recording medium; a magneto-resistive element which is magnetically coupled to the first and second portions of the first yoke and detects a magnetic recording signal; a second yoke formed on the first yoke so as to form a reproducing head gap between the first portion of the first yoke and the second yoke; and a third yoke provided between the first portion of the first yoke and the base so as to be magnetically coupled to the first portion of the first yoke. The reproducing head gap, the first portion of the first yoke, the magneto-resistive element, the second portion of the first yoke, ad the second yoke form a cut magnetic circuit.
摘要翻译：提供一种磁阻薄膜磁头，该磁头包括：基座; 设置在基座上并由间隙分隔成第一和第二部分的第一磁轭，第一部分包括与磁记录介质相对的一侧; 磁阻元件，其磁耦合到第一磁轭的第一和第二部分，并检测磁记录信号; 形成在第一磁轭上的第二磁轭，以在第一磁轭的第一部分和第二磁轭之间形成再现磁头间隙; 以及设置在第一磁轭的第一部分和基座之间的第三磁轭，以便磁耦合到第一磁轭的第一部分。再现磁头间隙，第一磁轭的第一部分，磁阻元件，第一磁轭的第二部分，第二磁轭形成切割磁路。

104. 发明授权

US06483136B1 Semiconductor integrated circuit and method of fabricating the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06483136B1
公开(公告)日：2002-11-19
申请号：US09446302
申请日：2000-04-14
申请人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
发明人： Makoto Yoshida , Takahiro Kumauchi , Yoshitaka Tadaki , Isamu Asano , Norio Hasegawa , Keizo Kawakita
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L27/10817
摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.
摘要翻译：在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案，在半导体衬底（1）的一个主表面上沿X方向线性地延伸。存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度，栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

105. 发明授权

US06291847B1 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06291847B1
公开(公告)日：2001-09-18
申请号：US09159754
申请日：1998-09-24
申请人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
发明人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10894
摘要： A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
摘要翻译：在形成正常存储单元的区域中，形成有浮雕单元的区域中的场氧化膜3比场氧化膜3宽，使得浮雕单元的场弛豫层8r比场弛豫层8更深的正电池，并且补充电池的源极和漏极（n型半导体区域）的耗尽层变宽以削弱结场。

106. 发明授权

US06278148B1 Semiconductor device having a shielding conductor 失效
标题翻译：具有屏蔽导体的半导体器件
公开(公告)号：US06278148B1
公开(公告)日：2001-08-21
申请号：US09040457
申请日：1998-03-18
申请人： Takao Watanabe , Takuya Fukuda , Norio Hasegawa
发明人： Takao Watanabe , Takuya Fukuda , Norio Hasegawa
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , G11C5/063 , G11C7/02 , G11C11/4097 , H01L23/5225 , H01L23/552 , H01L27/10805 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device that includes a dynamic memory and logic circuits that are integrated on a single chip and that can avoid noise problems and signal delay. The portion above the memory is shielded with a shielding conductor that is biased to an equipotential. Wirings between logical blocks and bonding pads or between logical blocks are passed over the conductive layer. Wiring for logic circuits can be done in the same metal wiring layer in which the shielding conductor is provided. The shielding conductor can have a mesh-like structure to improve its integrity and wirings can be passed over conductive portions of the shielding layer to be protected from noise. In addition to the dynamic memory, other memories and analog circuits can be used instead of or in combination with the dynamic memory.
摘要翻译：本发明涉及一种半导体器件，其包括集成在单个芯片上并且可以避免噪声问题和信号延迟的动态存储器和逻辑电路。存储器上方的部分用被偏置到等电位的屏蔽导体屏蔽。逻辑块和焊盘之间或逻辑块之间的布线通过导电层。逻辑电路的布线可以在设置有屏蔽导体的同一金属布线层中完成。屏蔽导体可以具有网状结构以改善其完整性，并且布线可以穿过屏蔽层的导电部分以防止噪声。除了动态存储器之外，可以使用其他存储器和模拟电路来代替动态存储器或与动态存储器组合使用。

107. 发明授权

US5851703A Photomask and pattern forming method employing the same 失效
公开(公告)号：US5851703A
公开(公告)日：1998-12-22
申请号：US904754
申请日：1997-08-01
申请人： Norio Hasegawa , Fumio Murai , Katsuya Hayano
发明人： Norio Hasegawa , Fumio Murai , Katsuya Hayano
IPC分类号： G03F1/00 , G03F1/26 , G03F1/29 , G03F1/32 , G03F1/68 , G03F7/20 , H01L21/027 , H01L21/30 , G03F9/00
CPC分类号： G03F1/32 , G03F1/26 , G03F1/29 , G03F7/70066 , G03F7/2022
摘要： A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.

108. 发明授权

US5791357A Support jig for thin circular objects 失效
标题翻译：用于薄圆形物体的支撑夹具
公开(公告)号：US5791357A
公开(公告)日：1998-08-11
申请号：US867450
申请日：1997-06-02
申请人： Norio Hasegawa
发明人： Norio Hasegawa
IPC分类号： B23Q3/06 , B65D85/86 , H01L21/304 , H01L21/306 , H01L21/673 , H01L21/683 , B08B3/04
CPC分类号： H01L21/67313 , Y10S134/902
摘要： A support jig for thin circular objects comprises two round rods, in each of which depressions, each having a substantially V-shaped cross section, are formed along the circumference of the round rod and perpendicularly to the center axis of the round rod and arranged along the center axis of the round rod. Thin circular objects are inserted into respective depressions formed in the round rods, so that the thin circular objects are supported by the support jig. A cut is formed in each of a plurality of side wall portions which define depressions such that the cut is symmetrical with respect to the perpendicular which connects the center of each of the supported thin circular objects and the center axis of each of the round bars. The support jig can stably retain thin circular objects, particularly wafers, upright so that their upper portions do not vibrate, and can reduce the areas subjected to surface tension.
摘要翻译：用于薄圆形物体的支撑夹具包括两个圆棒，每个具有大致V形截面的凹陷沿着圆棒的圆周形成并且垂直于圆棒的中心轴线并沿着圆棒的中心轴。薄的圆形物体被插入到形成在圆棒中的相应凹部中，使得薄的圆形物体被支撑夹具支撑。在形成凹部的多个侧壁部分中的每一个中形成切口，使得切口相对于连接每个支撑的薄圆形物体的中心和每个圆棒的中心轴线的垂直线对称。支撑夹具可以稳定地保持薄的圆形物体，特别是晶片，直立，使得它们的上部不振动，并且可以减少经受表面张力的区域。

109. 发明授权

US5691115A Exposure method, aligner, and method of manufacturing semiconductor integrated circuit devices 失效
标题翻译：半导体集成电路器件的曝光方法，对准器及其制造方法
公开(公告)号：US5691115A
公开(公告)日：1997-11-25
申请号：US546313
申请日：1995-10-20
申请人： Yoshihiko Okamoto , Tsuneo Terasawa , Akira Imai , Norio Hasegawa , Shinji Okazaki
发明人： Yoshihiko Okamoto , Tsuneo Terasawa , Akira Imai , Norio Hasegawa , Shinji Okazaki
IPC分类号： G03F1/00 , G03F1/26 , G03F1/30 , G03F1/60 , G03F7/20 , G03F9/00 , G03C5/00
CPC分类号： G03F9/70 , G03F1/26 , G03F1/30 , G03F1/60 , G03F7/70283 , G03F7/70466
摘要： To prevent positional shifts of the image forming plane during the exposure process using the two-layer phase shift mask, the height position of the semiconductor wafer 14 is moved in the optical axis direction according to the mask substrate thickness of the second component mask 12b, prior to performing the exposure process which uses the stacked-layer mask 12 that comprises a first component mask 12a formed with a pattern of light-shielding areas and light-transmitting areas and a second component mask 12b formed with a phase shift pattern to produce a phase shift in the transmitted light.
摘要翻译：为了防止在使用两层相移掩模的曝光处理期间图像形成面的位置偏移，半导体晶片14的高度位置根据第二分量掩模12b的掩模基板厚度沿光轴方向移动，在执行使用层叠掩模12的曝光处理之前，其包括形成有遮光区域和透光区域的图案的第一成分掩模12a和形成有相移图案的第二成分掩模12b，以产生透射光的相移。

110. 发明授权

US5677898A Disc cartridge container and apparatus having a plurality of cartridges arranged for simultaneous shutter opening closing 失效
标题翻译：碟形墨盒容器和装置具有多个墨盒，用于同时快门打开关闭
公开(公告)号：US5677898A
公开(公告)日：1997-10-14
申请号：US256208
申请日：1994-05-31
申请人： Norio Hasegawa , Masayasu Itoh , Hideaki Kawashimo
发明人： Norio Hasegawa , Masayasu Itoh , Hideaki Kawashimo
IPC分类号： G11B17/22 , G11B17/30 , G11B23/03 , G11B23/023
CPC分类号： G11B23/0323 , G11B17/221 , G11B17/30
摘要： A disc recording and/or reproducing apparatus in which a cartridge container has a number of disc cartridges loaded internal sections without stacking of the disc cartridges by arraying the disc cartridges in one plane in a matrix configuration includes a rotation supporting substrate supporting a driving part supporting substrate carrying a disc rotation driving mechanism and an optical pickup approached to and separated from the disc cartridge, a stationary part support substrate rotatably supporting the rotation supporting substrate, a rotation driving mechanism for rotating the rotation supporting mechanism, and a driving part supporting substrate lift mechanism for bringing the disc rotation driving mechanism and the optical pickup towards the disc cartridge or separating them away from the disc cartridge. Plural discs may be sequentially reproduced without displacing the disc cartridge by rotationally driving the rotating supporting substrate and bringing the disc rotationally driving mechanism and the optical pickup towards the disc cartridge or separating them away from the disc cartridge.
摘要翻译： PCT No.PCT / JP93 / 01405 Sec。 371日期1994年5月31日 102（e）日期1994年5月31日PCT提交1993年9月30日PCT公布。公开号WO94 / 08339 日期1994年04月14日一种盘式记录和/或再现装置，其中盒式存储器具有多个盘盒装载内部部分而不堆叠盘盒，通过将盘盒以矩阵形式排列在一个平面中，包括旋转支撑基板支撑承载盘旋转驱动机构的驱动部件和与盘盒接近并分离的光拾取器，可旋转地支撑旋转支撑基板的固定部支撑基板，用于旋转旋转支撑机构的旋转驱动机构，以及驱动部分支撑基板升降机构，用于将盘旋转驱动机构和光拾取器朝向盘盒，或将其从盘盒中分离。可以通过旋转驱动旋转的支撑基板并将盘旋转驱动机构和光学拾取器朝向盘盒或将其从盘盒中分离出来而顺序地再现多个盘。

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