专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08048614B2 Semiconductor integrated circuit device fabrication method 有权
标题翻译：半导体集成电路器件制造方法
公开(公告)号：US08048614B2
公开(公告)日：2011-11-01
申请号：US11463467
申请日：2006-08-09
申请人： Yoshihiko Okamoto , Masami Ogita
发明人： Yoshihiko Okamoto , Masami Ogita
IPC分类号： H01L21/00
CPC分类号： G03F1/62 , G03F1/48 , G03F7/70308 , G03F7/706 , G03F7/70983 , Y10S438/975 , Y10S438/976
摘要： A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.
摘要翻译：通过形成集成电路图案的掩模和缩小投影对准器，将具有比曝光光束的波长的一半更小的电路图案以优异的精度传输到半导体晶片平面上。通过超分辨率曝光的协同效应提高了半导体晶片上的电路图形的转印精度，其中由集成电路掩模的图案侧设置由透明介质制成的掩模罩，以便抑制还原的像差投影对准，以及在实施了平面化处理的半导体晶片的光致抗蚀剂侧上增加设置有由透明介质制成的晶片盖的光学还原投影透镜系统的实际孔径的数量的方法。

2. 发明申请

US20070117409A1 Aligner and Semiconductor Device Manufacturing Method Using the Aligner 有权
标题翻译：使用对准器的Aligner和半导体器件制造方法
公开(公告)号：US20070117409A1
公开(公告)日：2007-05-24
申请号：US11463467
申请日：2006-08-09
申请人： Yoshihiko Okamoto , Masami Ogita
发明人： Yoshihiko Okamoto , Masami Ogita
IPC分类号： H01L21/31
CPC分类号： G03F1/62 , G03F1/48 , G03F7/70308 , G03F7/706 , G03F7/70983 , Y10S438/975 , Y10S438/976
摘要： A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.
摘要翻译：通过形成集成电路图案的掩模和缩小投影对准器，将具有比曝光光束的波长的一半更小的电路图案以优异的精度传输到半导体晶片平面上。通过超分辨率曝光的协同效应提高了半导体晶片上的电路图形的转印精度，其中由集成电路掩模的图案侧设置由透明介质制成的掩模罩，以便抑制还原的像差投影对准，以及在实施了平面化处理的半导体晶片的光致抗蚀剂侧上增加设置有由透明介质制成的晶片盖的光学还原投影透镜系统的实际孔径的数量的方法。

3. 发明授权

US5973785A Method of forming light beam, apparatus therefor, method of measuring sizes using the same, method of inspecting appearance, method of measuring height, method of exposure, and method of fabricating semiconductor integrated circuits 失效
标题翻译：形成光束的方法，其设备，使用其尺寸的方法，外观检查方法，高度测量方法，曝光方法以及制造半导体集成电路的方法
公开(公告)号：US5973785A
公开(公告)日：1999-10-26
申请号：US568419
申请日：1995-12-06
申请人： Yoshihiko Okamoto
发明人： Yoshihiko Okamoto
IPC分类号： C23C16/48 , G01B11/06 , G01B11/28 , G01N21/88 , G01N21/94 , G01N21/95 , G02B21/00 , G02B27/58 , G11B7/135 , G11B7/26 , H01L21/027 , G01B9/02
CPC分类号： G11B7/1365 , G01B11/0608 , G01B11/28 , G01N21/8806 , G02B21/0056 , G02B21/006 , G02B27/58 , G11B7/1381 , G11B7/261
摘要： Technology for forming a fine light beam having a size smaller than the theoretical limit determined by the wavelength of light and characteristics of an objective lens. A beam distribution shifter having two light transmission regions is disposed between a source of light and an objective lens, a phase shifter is provided on one of the two light transmission regions to divide the light passing through the beam distribution shifter into two light fluxes having phases opposite to each other, and the two light fluxes are focused through the objective lens to form a fine light beam having a size smaller than the theoretical limit determined by the wavelength of the light and characteristics of the objective lens due to destructive interference between the two light fluxes.
摘要翻译：用于形成尺寸小于由光的波长和物镜的特性确定的理论极限的精细光束的技术。具有两个光透射区域的光束分配移位器设置在光源和物镜之间，在两个光透射区域中的一个上设置移相器，以将通过光束分配移位器的光分成具有相位的两个光束并且两个光束通过物镜聚焦以形成尺寸小于由光的波长确定的理论极限和由于两者之间的相消干涉而导致的物镜特性的细小光束光通量。

4. 发明授权

US5837423A Semiconductor IC device fabricating method 失效
标题翻译：半导体IC器件制造方法
公开(公告)号：US5837423A
公开(公告)日：1998-11-17
申请号：US804922
申请日：1997-02-24
申请人： Yoshihiko Okamoto
发明人： Yoshihiko Okamoto
IPC分类号： G03F7/004 , G03F7/09 , G03F7/11 , G03F7/20 , G03F7/38 , H01L21/027 , H01L21/033 , H01L21/311 , H01L21/3213 , G03C5/00
CPC分类号： H01L21/0277 , G03F7/0045 , G03F7/093 , G03F7/2059 , H01L21/0331 , H01L21/31144 , H01L21/32139 , G03F7/11 , G03F7/38 , Y10S148/046 , Y10S148/137 , Y10S438/949
摘要： Either a chemical amplification positive electron beam resist film or a chemical amplification negative electron beam resist film is used selectively according to an IC fabricating process when forming a minute IC pattern by using, as a mask, a resist pattern formed by irradiating the chemical amplification electron beam resist film formed on a semiconductor wafer with an electron beam, to form the minute IC pattern quickly in a high accuracy and to carry out an electron beam direct writing at a high throughput. The chemical amplification electron beam resist film is coated with a conductive polymer film before irradiating the same with the electron beam to prevent the charging-up of the chemical amplification electron beam resist film and to stabilize the chemical amplification electron beam resist film during a electron beam writing process.
摘要翻译：当通过使用通过照射化学放大电子形成的抗蚀图案作为掩模来形成微小IC图案时，根据IC制造工艺选择性地使用化学放大正电子束抗蚀剂膜或化学放大负电子束抗蚀剂膜形成在具有电子束的半导体晶片上的光束抗蚀剂膜，以高精度快速形成微小的IC图案，并以高通量执行电子束直接写入。化学放大电子束抗蚀剂膜在用电子束照射之前涂覆有导电聚合物膜，以防止化学放大电子束抗蚀剂膜的充电并且在电子束期间稳定化学放大电子束抗蚀剂膜写作过程。

5. 发明授权

US5786112A Photomask manufacturing process and semiconductor integrated circuit device manufacturing process using the photomask 失效
标题翻译：光掩模制造工艺和使用光掩模的半导体集成电路器件制造工艺
公开(公告)号：US5786112A
公开(公告)日：1998-07-28
申请号：US664865
申请日：1996-06-17
申请人： Yoshihiko Okamoto , Yasuhiro Koizumi
发明人： Yoshihiko Okamoto , Yasuhiro Koizumi
IPC分类号： G03F1/30 , G03F1/36 , G03F1/54 , G03F1/68 , G03F1/72 , G03F1/84 , H01L21/027 , G03F9/00
CPC分类号： G03F1/84 , G03F1/26
摘要： In order to improve the inspection efficiency of a photomask having a phase shifter pattern, the inspection of the photomask having the phase shifter pattern is divided into three steps, an anomaly extraction step, a first anomaly discrimination step and a second anomaly discrimination step. These inspection steps are performed at different inspection regions. An anomaly extraction station 7 for the anomaly extraction inspects the presence or absence of an anomaly for all the regions of the photomask 1. An anomaly discrimination station 8 for the anomaly discrimination classifies the content of the anomaly. A phase difference measurement station 9 for the anomaly discrimination measures the phase difference error.
摘要翻译：为了提高具有移相器图案的光掩模的检查效率，将具有移相器图案的光掩模的检查分为三个步骤，异常提取步骤，第一异常判别步骤和第二异常判别步骤。这些检查步骤在不同的检查区域进行。用于异常提取的异常提取站7检查光掩模1的所有区域的异常的存在或不存在。异常鉴别站8用于对异常的内容进行分类。用于异常辨别的相位差测量站9测量相位差误差。

6. 发明授权

US5631108A Mask for manufacturing semiconductor device and method of manufacture thereof 失效
标题翻译：用于制造半导体器件的掩模及其制造方法
公开(公告)号：US5631108A
公开(公告)日：1997-05-20
申请号：US449926
申请日：1995-05-25
申请人： Yoshihiko Okamoto
发明人： Yoshihiko Okamoto
IPC分类号： G03F1/68 , G03F1/00 , G03F1/26 , G03F1/29 , G03F1/30 , G03F1/40 , G03F1/80 , G03F7/20 , H01L21/027 , H01L21/30 , G03F9/00
CPC分类号： G03F1/29 , G03F1/30 , G03F1/26 , Y10S438/948
摘要： The present invention relates to a microminiaturization technique to achieve the miniaturization and higher integration of IC chip and to the improvement of a mask used in its manufacturing process. In other words, the phases of lights transmitted through the mask is controlled within one mask pattern. Specifically, a transparent film is formed in such a manner that it covers a mask pattern along a pattern formed by magnifying or demagnifying the mask pattern or otherwise a groove is formed in a mask substrate. A phase difference of 180.degree. is generated between the lights transmitted through the mask substrate and the transparent film or the groove, causing interference with each light to offset each other. Therefore, the pattern transferred onto a wafer has an improved resolution, being used in the invention.
摘要翻译：本发明涉及实现IC芯片的小型化和更高集成化以及改进其制造工艺中使用的掩模的微型化技术。换句话说，通过掩模传输的光的相位被控制在一个掩模图案内。具体地，透明膜形成为沿着通过放大或缩小掩模图案而形成的图案覆盖掩模图案，否则在掩模基板中形成凹槽。在透过掩模基板的光与透明膜或槽之间产生180°的相位差，导致每个光的干涉彼此抵消。因此，转印到晶片上的图案具有改进的分辨率，用于本发明。

7. 发明授权

US5557314A Exposure method and pattern data preparation system therefor, pattern data preparation method and mask as well as exposure apparatus 失效
标题翻译：曝光方法和图案数据准备系统，图案数据准备方法和掩模以及曝光装置
公开(公告)号：US5557314A
公开(公告)日：1996-09-17
申请号：US77411
申请日：1993-06-16
申请人： Yoshihiko Okamoto , Haruo Yoda , Ikuo Takada , Yukinobu Shibata , Akira Hirakawa , Norio Saitou , Shinji Okazaki , Fumio Murai
发明人： Yoshihiko Okamoto , Haruo Yoda , Ikuo Takada , Yukinobu Shibata , Akira Hirakawa , Norio Saitou , Shinji Okazaki , Fumio Murai
IPC分类号： G03F7/20 , H01J37/305 , H01J37/317 , H01L21/027 , B41J2/435
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3174 , H01J2237/31766 , H01J2237/31776
摘要： Selective pattern exposure with high reliability is made possible by a desired pattern of repeated pattern and a non-repeated pattern. Exposure technology is obtained to enable improvement of preparation efficiency of pattern data and to secure inspection of an aperture pattern. With the invention, an electron beam is used as focused beam, and a pattern exposure apparatus of a batch transfer system for transferring repeated pattern and non-repeated pattern of plural graphics of a semiconductor integrated circuit or the like comprises an EB drawing section for controlling the beam and irradiating beam onto a sample, a control I/O section, a drawing control section and a data storage section. In the EB drawing section, a semiconductor wafer is mounted on a platform, and in the path of the electron beam from the electron beam source to the stage, a first mask, a blanking electrode, an electron lens, a first deflector, a second deflector, a second mask and a third deflector are installed.
摘要翻译：通过重复图案和非重复图案的期望图案，可以实现高可靠性的选择性图案曝光。获得曝光技术以提高图案数据的准备效率并确保孔径图案的检查。通过本发明，电子束被用作聚焦光束，并且用于传送半导体集成电路等的多个图形的重复图案和非重复图案的批传送系统的图案曝光装置包括用于控制的EB绘图部分光束和照射光束到样品上，控制I / O部分，绘图控制部分和数据存储部分。在EB绘图部分中，半导体晶片安装在平台上，并且在从电子束源到舞台的电子束的路径中，安装第一掩模，消隐电极，电子透镜，第一偏转器，第二透镜偏转器，第二掩模和第三偏转器。

8. 发明授权

US5502001A Method of forming light beam and method of fabricating semiconductor integrated circuits 失效
标题翻译：形成光束的方法和制造半导体集成电路的方法
公开(公告)号：US5502001A
公开(公告)日：1996-03-26
申请号：US218233
申请日：1994-03-28
申请人： Yoshihiko Okamoto
发明人： Yoshihiko Okamoto
IPC分类号： C23C16/48 , G01B11/06 , G01B11/28 , G01N21/88 , G01N21/94 , G01N21/95 , G02B21/00 , G02B27/58 , G11B7/135 , G11B7/26 , H01L21/027 , H01L21/26
CPC分类号： G11B7/1365 , G01B11/0608 , G01B11/28 , G01N21/8806 , G02B21/0056 , G02B21/006 , G02B27/58 , G11B7/1381 , G11B7/261
摘要： Technology for forming a fine light beam having a size smaller than the theoretical limit determined by the wavelength of light and characteristics of an objective lens. A beam distribution shifter having two light transmission regions is disposed between a source of light and an objective lens, a phase shifter is provided on one of the two light transmission regions to divide the light passing through the beam distribution shifter into two light fluxes having phases opposite to each other, and the two light fluxes are focused through the objective lens to form a fine light beam having a size smaller than the theoretical limit determined by the wavelength of the light and characteristics of the objective lens due to destructive interference between the two light fluxes.
摘要翻译：用于形成尺寸小于由光的波长和物镜的特性确定的理论极限的精细光束的技术。具有两个光透射区域的光束分配移位器设置在光源和物镜之间，在两个光透射区域中的一个上设置移相器，以将通过光束分配移位器的光分成具有相位的两个光束并且两个光束通过物镜聚焦以形成尺寸小于由光的波长确定的理论极限和由于两者之间的相消干涉而导致的物镜特性的细小光束光通量。

9. 发明授权

US5418092A Process for manufacturing semiconductor integrated circuit device, exposure method and mask for the process 失效
标题翻译：用于制造半导体集成电路器件的工艺，曝光方法和掩模
公开(公告)号：US5418092A
公开(公告)日：1995-05-23
申请号：US897455
申请日：1992-06-10
申请人： Yoshihiko Okamoto
发明人： Yoshihiko Okamoto
IPC分类号： G03F1/00 , G03F1/26 , G03F1/29 , G03F1/30 , G03F1/60 , G03F1/68 , G03F7/20 , G03F9/00 , H01L21/027 , H01L21/30
CPC分类号： G03F1/30 , G03F1/26 , G03F1/60 , G03F7/70283 , G03F7/70466 , G03F9/70
摘要： A mask and an exposure method are provided in which a wafer is irradiated with light transmitted through the mask formed with a predetermined pattern having a shielding region and a transmissive region, to transfer the pattern of said mask. In particular, the mask includes a first mask and a second mask. The first mask is formed with a pattern having a shielding region and a transparent region, while the second mask is formed with a pattern having a phase shifter for introducing a phase difference in a portion of the transmission light. The first and second masks are superposed relative to one another over the wafer so that a clear image may be focused on said wafer by making use of interference of said transmission light caused by said first and second mask. It is to be noted that this arrangement also has the advantage of not transferring images of foreign substances stuck on the back of the mask, to the wafer.
摘要翻译：提供了一种掩模和曝光方法，其中通过掩模和透射区域以预定图案形成的透光膜照射晶片，以转印所述掩模的图案。具体地，掩模包括第一掩模和第二掩模。第一掩模形成有具有屏蔽区域和透明区域的图案，而第二掩模形成有具有用于在透射光的一部分中引入相位差的移相器的图案。第一和第二掩模相对于彼此叠置在晶片上，使得透明图像可以通过利用由所述第一和第二掩模引起的所述透射光的干涉而聚焦在所述晶片上。应当注意，该布置还具有不将粘附在掩模背面的异物的图像转印到晶片的优点。

10. 发明授权

US5311026A Charged particle beam lithography system and method therefor 失效
标题翻译：带电粒子束光刻系统及其方法
公开(公告)号：US5311026A
公开(公告)日：1994-05-10
申请号：US858575
申请日：1992-03-27
申请人： Norio Saitou , Yoshihiko Okamoto , Takashi Yamazaki , Hideo Todokoro
发明人： Norio Saitou , Yoshihiko Okamoto , Takashi Yamazaki , Hideo Todokoro
IPC分类号： H01L21/027 , H01J37/304
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J37/3045 , H01J2237/1505 , H01J2237/3045 , H01J2237/31776
摘要： The present invention relates to a system for drawing patterns on a wafer by using a charged particle beam such as an electron beam, in which a complicated prealigning mechanism used for mounting the wafer on a stage is omitted. Instead, according to the present system, rotation of the wafer is detected and a shaped beam is rotated by an amount corresponding to the value detected. Subsequently, a predetermined pattern is drawn on the substrate. The system includes a detecting device for detecting the rotation of the wafer by using an orientation flat or adjusting marks; a computer for storing a value corresponding to the rotation thus detected; a rotating lens control circuit for receiving data from the computer; and a rotating lens.
摘要翻译：本发明涉及一种通过使用诸如电子束的带电粒子束在晶片上绘制图形的系统，其中省略了用于将晶片安装在平台上的复杂预对准机构。相反，根据本系统，检测晶片的旋转，并且将成形光束旋转与所检测的值对应的量。随后，在衬底上绘制预定图案。该系统包括用于通过使用取向平面或调整标记来检测晶片的旋转的检测装置; 用于存储与所检测的旋转对应的值的计算机; 用于从计算机接收数据的旋转透镜控制电路; 和旋转透镜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式