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91. 发明申请

US20050062547A1 Method and apparatus to generate signals using two or more phase locked loops 审中-公开
标题翻译：使用两个或多个锁相环生成信号的方法和装置
公开(公告)号：US20050062547A1
公开(公告)日：2005-03-24
申请号：US10664850
申请日：2003-09-22
申请人： Yossi Reuven
发明人： Yossi Reuven
IPC分类号： H03L7/197 , H03L7/23 , H03L7/00
CPC分类号： H03L7/1974 , H03L7/23
摘要： Briefly, according to embodiments of the invention, there is provided a method and an apparatus that may include a first phase locked loop to set a frequency of an output signal of a first voltage controlled oscillator and a second phase locked loop to receive the output signal of the first voltage controlled oscillator and to lock a second voltage controlled oscillator to the frequency of the output signal provided by the first voltage controlled oscillator.
摘要翻译：简而言之，根据本发明的实施例，提供了一种方法和装置，其可以包括第一锁相环，以设置第一压控振荡器和第二锁相环的输出信号的频率，以接收输出信号并且将第二压控振荡器锁定到由第一压控振荡器提供的输出信号的频率。

92. 发明申请

US20050057311A1 Clock generation system 失效
标题翻译：时钟发生系统
公开(公告)号：US20050057311A1
公开(公告)日：2005-03-17
申请号：US10919634
申请日：2004-08-17
申请人： Masayu Fujiwara
发明人： Masayu Fujiwara
IPC分类号： G11B20/14 , H03L7/00 , H03L7/07 , H03L7/099 , H03L7/183 , H03L7/197 , H03L7/23
CPC分类号： H03L7/1974 , H03L7/23
摘要： A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.
摘要翻译：提供了分频参考频率时钟作为相位比较器的参考输入。具有与另一参考频率时钟相关联的频率的可控振荡器的振荡频率信号由分频因子切换型比较输入分频电路进行频率分频。所得到的分频时钟作为比较输入提供给相位比较器。比较输入分频电路的分频因子基于分频因子控制信号从一个切换到另一个，以产生相对于另一参考频率时钟具有预定频率比的振荡频率信号。因此，以足够的S / N比获得符合MPEG格式的27MHz，33.8688MHz和36.864MHz的三个参考频率时钟。

93. 发明申请

US20050042996A1 Apparatus for generating multiple clock signals of different frequency characteristics 有权
标题翻译：用于产生不同频率特性的多个时钟信号的装置
公开(公告)号：US20050042996A1
公开(公告)日：2005-02-24
申请号：US10496524
申请日：2002-11-04
申请人： Nadim Khlat , Cor Voorwinden
发明人： Nadim Khlat , Cor Voorwinden
IPC分类号： G06F1/04 , G06F1/08 , H03L7/08 , H03L7/197 , H03L7/22 , H03L7/23 , H04B1/16 , H04B1/38 , H04B1/06 , H04B1/26 , H04B7/00 , H04M1/00
CPC分类号： H03L7/23 , H03L7/0802 , H03L7/1976
摘要： A terminal includes at least one wireless communication application module (1) and a plurality of further application modules (4, 5, 6, 8). Multiple radio frequency clock signals are generated for the different modules having respective clock frequency characteristics and including at least first and second clock frequencies that are not integral multiples nor sub-multiples of each other nor of a third frequency. The clock generation comprises reference frequency means (14), fractional-N phase-locked loop frequency synthesizer means (15) responsive to the reference frequency means, and different automatic frequency control means for adjusting clock frequencies relative to received signals. The reference frequency means (14) is arranged to supply a common reference frequency signal to a plurality of the fractional-N phase-locked loop frequency synthesizer means (17, 18, 19, 25, 26, 41,42) that supply the first and second clock frequencies respectively for the application modules. Selective activation means (30,52) selectively activates and de-activates the phase lock loop means as required by the corresponding application module or modules.
摘要翻译：终端包括至少一个无线通信应用模块（1）和多个其他应用模块（4,5,6,8）。为具有各自时钟频率特性的不同模块生成多个射频时钟信号，并且至少包括第一和第二时钟频率，其不是整数倍，也不是彼此的子倍数，也包括第三频率。时钟生成包括响应于参考频率装置的参考频率装置（14），分数N锁相环频率合成器装置（15）和用于相对于接收信号调整时钟频率的不同的自动频率控制装置。参考频率装置（14）被布置成将公共参考频率信号提供给多个分数N个锁相环频率合成器装置（17,18,19,25,26,41,42），其提供第一和第二时钟频率分别用于应用模块。选择性激活装置（30,52）根据相应的应用模块或模块的要求有选择地激活和去激活锁相环装置。

94. 发明授权

US06853222B2 Phase locked loop circuit having main and auxiliary frequency dividers and multiple phase comparisons 失效
标题翻译：锁相环电路具有主分频器和辅助分频器以及多相比较
公开(公告)号：US06853222B2
公开(公告)日：2005-02-08
申请号：US10262191
申请日：2002-10-01
申请人： Yasuaki Sumi
发明人： Yasuaki Sumi
IPC分类号： H03K23/66 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/191 , H03L7/23 , H03L7/06
CPC分类号： H03K23/665 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/191 , H03L7/23
摘要： A PLL circuit including a generating means (3) for generating a plurality of reference signals (fR1 to fR8) having mutually differing phases, a main frequency divider (30) dividing an output signal (fVCO) of a voltage-controlled oscillator (29) by a frequency-division ratio of N1, an auxiliary frequency divider (31) dividing an output (fV′) of the main frequency divider by a frequency-division ratio of N2, a distribution circuit (32) distributing an output (Q1a, Q2a, Q3a) of the auxiliary frequency divider as a plurality of feedback signals (fV1 to fV8), and phase comparators (12 to 19) comparing the reference signals with the feedback signals to output error signals (ER1 to ER8). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.
摘要翻译：一种PLL电路，包括用于产生具有相互不同相位的多个参考信号（fR1至fR8）的发生装置（3），分压电压控制振荡器（29）的输出信号（fVCO）的主分频器（30）通过N1的分频比，将主分频器的输出（fV'）除以N2的分频比的辅助分频器（31），分配输出（Q1a，Q2a）的分配电路（32），Q3a）作为多个反馈信号（fV1〜fV8），以及将参考信号与反馈信号进行比较以输出误差信号（ER1〜ER8）的相位比较器（12〜19）。主分频器和辅助分频器分别由可变分频器或计数器组成。

95. 发明申请

US20040258188A1 Clock and data recovery device coping with variable data rates 有权
标题翻译：时钟和数据恢复设备应对可变数据速率
公开(公告)号：US20040258188A1
公开(公告)日：2004-12-23
申请号：US10789217
申请日：2004-02-27
发明人： Chan-Yul Kim , Jun-Ho Koh , Yun-Ju Oh
IPC分类号： H03D003/24
CPC分类号： H03L7/23 , H03L7/087 , H03L7/14 , H04L7/0087 , H04L7/033
摘要： A clock and data recovery (CDR) device is disclosed that is capable of recovering a clock signal from a data signal that has a variable data rate. The CDR device includes a reference clock generating section for dividing a basic clock by a first predetermined value P, synchronizing the clock and multiplying the clock by a second predetermined value Q to generate a reference clock corresponding to the variable data rate; a clock and data recovery section for receiving the transmitted data, recovering a clock and data from the received data and outputting the recovered clock and data; and a control section for generating a control signal according to the variable data rate and sending the signal to the reference clock generating section and the clock and data recovery section.
摘要翻译：公开了一种能够从具有可变数据速率的数据信号中恢复时钟信号的时钟和数据恢复（CDR）设备。 CDR设备包括：参考时钟产生部分，用于将基本时钟除以第一预定值P，使时钟同步并将时钟乘以第二预定值Q，以产生对应于可变数据速率的参考时钟; 时钟和数据恢复部分，用于接收所发送的数据，从所接收的数据中恢复时钟和数据并输出恢复的时钟和数据; 以及控制部分，用于根据可变数据速率产生控制信号，并将信号发送到参考时钟产生部分和时钟和数据恢复部分。

96. 发明授权

US06833764B1 Apparatus and method for synthesizing a frequency using vernier dividers 有权
标题翻译：使用游标分频器合成频率的装置和方法
公开(公告)号：US06833764B1
公开(公告)日：2004-12-21
申请号：US10320851
申请日：2002-12-16
申请人： Gregory L. Dean
发明人： Gregory L. Dean
IPC分类号： H03L700
CPC分类号： H03L7/23
摘要： A PLL frequency synthesizer tunable in small step sizes that comprises: 1) a first PLL circuit comprising: i) a first feedforward frequency divider that receives an F(in) frequency and generates an F1 frequency, where F1=F(in)/P, ii) a first PLL core that receives the F1 frequency and generates an F2 frequency, where F2=(P+&Dgr;p)F1, and iii) a first feedback frequency divider that receives the F2 frequency and generates a first feedback signal having frequency F2/(P+&Dgr;p); and 2) a second PLL circuit comprising: i) a second feedforward frequency divider that receives the F2 frequency and generates an F3 frequency, where F3=F2/(N+&Dgr;n), ii) a second PLL core that receives the F3 frequency and generates an F(out) frequency, where F(out)=(N)F3, and iii) a second feedback frequency divider that receives the F(out) frequency and generates a second feedback signal having frequency F(out)/(N).
摘要翻译：一种可以小步长调节的PLL频率合成器，包括：1）第一PLL电路，包括：i）接收F（in）频率并产生F1频率的第一前馈分频器，其中F1 = F（in）/ P ，ii）接收F1频率并产生F2频率的第一PLL核心，其中F2 =（P + Deltap）F1，以及iii）第一反馈分频器，其接收F2频率并产生具有频率F2的第一反馈信号 /（P + Deltap）; 以及2）第二PLL电路，包括：i）第二前馈分频器，其接收F2频率并产生F3频率，其中F3 = F2 /（N + Deltan），ii）接收F3频率的第二PLL核心和产生F（out）频率，其中F（out）=（N）F3，以及iii）第二反馈分频器，其接收F（输出）频率并产生具有频率F（out）/（N ）。

97. 发明申请

US20040165690A1 Synchronizing method and apparatus 有权
标题翻译：同步方法和装置
公开(公告)号：US20040165690A1
公开(公告)日：2004-08-26
申请号：US10789546
申请日：2004-02-27
申请人： Broadcom Corporation
发明人： Tarek Kaylani , Fang Lu , Henry Samueli
IPC分类号： H04K001/00 , H04L025/00
CPC分类号： G06F5/14 , G06F1/025 , G06F5/12 , G06F2205/061 , G06F2205/126 , H03L7/07 , H03L7/081 , H03L7/085 , H03L7/0996 , H03L7/23 , H04J3/062
摘要： To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output signal is compared with the bunched pulse train. The selected phase shifted signal is changed responsive to the comparison so the output signal occurs at the average frequency of the bunched pulse train. The oscillator is formed as a plurality of differential amplifier stages having equal controllable delays. The stages are connected together to form a ring oscillator. The output signal is compared with the bunched pulse train through a FIFO. A signal representative of the state of the FIFO is used as an error signal to control the selection of the phase shifted signal to be used as the output signal. A phase locked loop that synchronizes the phase shifted signal generating oscillator to a frequency reference is nested in the control loop that selects one of the phase shifted signals as the output signal.
摘要翻译：为了使定期发生的脉冲串与聚束脉冲串的平均值同步，振荡器以给定频率产生多个不同的相移信号。选择一个相移信号作为输出信号。将输出信号与聚束脉冲串进行比较。所选择的相移信号响应于比较而改变，因此输出信号以聚束脉冲串的平均频率发生。振荡器形成为具有相同可控延迟的多个差分放大器级。这些级连接在一起以形成环形振荡器。输出信号通过FIFO与聚束脉冲序列进行比较。代表FIFO状态的信号被用作误差信号，以控制用作输出信号的相移信号的选择。将相移信号产生振荡器与频率基准同步的锁相环嵌套在选择相移信号之一作为输出信号的控制回路中。

98. 发明申请

US20040157565A1 Frequency generation in a wireless communication system 审中-公开
标题翻译：无线通信系统中的频率产生
公开(公告)号：US20040157565A1
公开(公告)日：2004-08-12
申请号：US10765305
申请日：2004-01-26
发明人： Karl E. Moerder
IPC分类号： H04B001/40
CPC分类号： H04N21/435 , G06F11/0757 , G06F11/1441 , H03J7/065 , H03L7/23 , H04B1/40 , H04B7/18582 , H04L7/0029 , H04L7/04 , H04L27/22 , H04L29/06 , H04L69/08 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/166 , H04L69/168 , H04N21/235 , H04N21/23614 , H04N21/2385 , H04N21/4348 , H04N21/4381 , H04N21/6143 , H04N21/64322 , H04W28/18
摘要： A communication system extracts a received modulation frequency from baseband modulation. This frequency is used as a reference to control the output of a variable oscillator. The output of the variable oscillator may be used to generate a transmit upconversion frequency, and may also be used to perform a downconversion from IF to baseband during receive operations.
摘要翻译：通信系统从基带调制中提取接收到的调制频率。该频率用作控制可变振荡器的输出的参考。可变振荡器的输出可以用于产生发射上变频频率，并且还可以用于在接收操作期间执行从IF到基带的下变频。

99. 发明授权

US06768362B1 Fail-safe zero delay buffer with automatic internal reference 有权
标题翻译：具有自动内部参考值的故障安全零延迟缓冲器
公开(公告)号：US06768362B1
公开(公告)日：2004-07-27
申请号：US09928818
申请日：2001-08-13
申请人： Eric N. Mann , John J. Wunner
发明人： Eric N. Mann , John J. Wunner
IPC分类号： H03L700
CPC分类号： H03L7/23 , H03L7/087 , H03L7/089 , H03L7/099
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为接收第一参考信号并产生第二参考信号。第二参考信号的频率和相位可以（i）响应于第一参考信号而被调整，并且（ii）当第一参考信号丢失时保持。第二电路可以被配置为响应于第二参考信号和一个或多个输出信号中的一个而产生一个或多个输出信号。一个或多个输出信号可以相对于第一参考信号具有受控和/或基本为零的延迟。

100. 发明授权

US06759910B2 Phase locked loop (PLL) frequency synthesizer and method 失效
公开(公告)号：US06759910B2
公开(公告)日：2004-07-06
申请号：US10267027
申请日：2002-10-07
申请人： Danny F. Ammar , Ronald D. Graham
发明人： Danny F. Ammar , Ronald D. Graham
IPC分类号： H03L707
CPC分类号： H03L7/23
摘要： A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

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