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91. 发明授权

US06489226B2 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY 有权
标题翻译：形成接触开口的半导体处理方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（DRAM）电路的方法
公开(公告)号：US06489226B2
公开(公告)日：2002-12-03
申请号：US09995373
申请日：2001-11-26
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

92. 发明授权

US06420249B1 Method for fabricating a floating gate semiconductor device 有权
标题翻译：浮栅半导体器件的制造方法
公开(公告)号：US06420249B1
公开(公告)日：2002-07-16
申请号：US09536931
申请日：2000-03-27
申请人： Trung Tri Doan , Tyler A. Lowrey
发明人： Trung Tri Doan , Tyler A. Lowrey
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
摘要翻译：提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。该器件包括具有电隔离的有源区的硅衬底。栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。

93. 发明授权

US06404665B1 Compositionally modified resistive electrode 有权
公开(公告)号：US06404665B1
公开(公告)日：2002-06-11
申请号：US09675803
申请日：2000-09-29
申请人： Tyler A. Lowrey , Daniel Xu , Chien Chiang , Patrick J. Neschleba
发明人： Tyler A. Lowrey , Daniel Xu , Chien Chiang , Patrick J. Neschleba
IPC分类号： G11C1100
CPC分类号： H01L29/685 , G11C13/0004 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a first resistivity value and a second material having a different second resistivity value formed by exposing the first material to a gaseous ambient.

94. 发明授权

US06391756B1 Semiconductor processing methods of forming contact openings 有权
标题翻译：形成接触开口的半导体加工方法
公开(公告)号：US06391756B1
公开(公告)日：2002-05-21
申请号：US09387040
申请日：1999-08-31
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被移除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

95. 发明授权

US06368887B1 Method of monitoring a process of manufacturing a semiconductor wafer including hemispherical grain polysilicon 失效
标题翻译：监测制造包括半球形晶粒多晶硅的半导体晶片的工艺的方法
公开(公告)号：US06368887B1
公开(公告)日：2002-04-09
申请号：US09576650
申请日：2000-05-22
申请人： Tyler A. Lowrey , Klaus F. Schuegraf , Randhir P. S. Thakur
发明人： Tyler A. Lowrey , Klaus F. Schuegraf , Randhir P. S. Thakur
IPC分类号： H01L2166
CPC分类号： H01L22/20 , H01L22/12
摘要： A method of monitoring a process of manufacturing a semiconductor wafer including an area of hemispherical grain polysilicon, the method comprising providing a probe including a liquid conductor; and performing a capacitance-voltage measurement with the probe, using a quasi-static measurement method, to determine capacitance-voltage characteristics at the area of hemispherical grain polysilicon.
摘要翻译：一种监视半导体晶片制造工艺的方法，所述半导体晶片包括半球形晶粒多晶硅的区域，所述方法包括提供包括液体导体的探针; 并使用准静态测量方法用探头进行电容电压测量，以确定半球形晶粒多晶硅区域的电容 - 电压特性。

96. 发明授权

US6124163A Integrated chip multiplayer decoupling capacitors 有权
标题翻译：集成芯片多人去耦电容器
公开(公告)号：US6124163A
公开(公告)日：2000-09-26
申请号：US459131
申请日：1999-12-10
申请人： Brian M. Shirley , Stephen L. Casper , Tyler A. Lowrey , Kevin G. Duesman
发明人： Brian M. Shirley , Stephen L. Casper , Tyler A. Lowrey , Kevin G. Duesman
IPC分类号： H01L21/02 , H01L27/06 , H01L27/105 , H01L29/92 , H01L21/283
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译：公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。

97. 发明授权

US5854102A Vertical diode structures with low series resistance 失效
标题翻译：具有低串联电阻的垂直二极管结构
公开(公告)号：US5854102A
公开(公告)日：1998-12-29
申请号：US932791
申请日：1997-09-05
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L21/329 , H01L27/08 , H01L29/861 , H01L21/8234
CPC分类号： H01L29/66136 , H01L27/0814 , H01L29/861 , Y10S257/91 , Y10S438/979
摘要： A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了具有延伸穿过绝缘层并与硅晶片上的有源区接触的二极管开口的垂直二极管。硅化钛层覆盖二极管开口的内表面并接触有源区。二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。顶部由底部界定，以便不与硅化钛层接触。对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

98. 发明授权

US5767005A Method for fabricating a flash EEPROM 失效
公开(公告)号：US5767005A
公开(公告)日：1998-06-16
申请号：US532997
申请日：1995-09-25
申请人： Trung Tri Doan , Tyler A. Lowrey
发明人： Trung Tri Doan , Tyler A. Lowrey
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825 , H01L21/28273
摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

99. 发明授权

US5739576A Integrated chip multilayer decoupling capacitors 失效
标题翻译：集成芯片多层去耦电容器
公开(公告)号：US5739576A
公开(公告)日：1998-04-14
申请号：US539855
申请日：1995-10-06
申请人： Brian M. Shirley , Stephen L. Casper , Tyler A. Lowrey , Kevin G. Duesman
发明人： Brian M. Shirley , Stephen L. Casper , Tyler A. Lowrey , Kevin G. Duesman
IPC分类号： H01L21/02 , H01L27/06 , H01L27/105 , H01L29/92 , H01L29/00
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译：公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。

100. 发明授权

US5653619A Method to form self-aligned gate structures and focus rings 失效
标题翻译：形成自对准栅极结构和聚焦环的方法
公开(公告)号：US5653619A
公开(公告)日：1997-08-05
申请号：US300985
申请日：1994-09-06
申请人： Eugene H. Cloud , Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
发明人： Eugene H. Cloud , Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
IPC分类号： H01J9/02 , H01J1/30
CPC分类号： H01J9/025 , H01J2209/0226 , H01J2329/00
摘要： A selective etching and chemical mechanical planarization process is employed for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays. The process is employed to construct an emission grid whereby the gate structure is capable of producing a field strength at the cathode tip sufficient to generate electron emission. The gate is disposed at a location above the tip such that the gate physically intercepts the outermost lateral portions of the beam, yet does not induce a significant electrostatic outward divergence of the beam, thereby reducing the cross-section of the beam.
摘要翻译：采用选择性蚀刻和化学机械平面化方法来形成围绕用于场发射显示器的电子发射尖端的自对准栅极和聚焦环结构。该方法用于构建发射栅极，由此栅极结构能够在阴极尖端产生足以产生电子发射的场强。门设置在尖端上方的位置，使得栅极物理地截取梁的最外侧部分，但不会引起梁的显着的静电向外发散，从而减小梁的横截面。

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