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1. 发明授权

US5653619A Method to form self-aligned gate structures and focus rings 失效
标题翻译：形成自对准栅极结构和聚焦环的方法
公开(公告)号：US5653619A
公开(公告)日：1997-08-05
申请号：US300985
申请日：1994-09-06
申请人： Eugene H. Cloud , Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
发明人： Eugene H. Cloud , Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
IPC分类号： H01J9/02 , H01J1/30
CPC分类号： H01J9/025 , H01J2209/0226 , H01J2329/00
摘要： A selective etching and chemical mechanical planarization process is employed for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays. The process is employed to construct an emission grid whereby the gate structure is capable of producing a field strength at the cathode tip sufficient to generate electron emission. The gate is disposed at a location above the tip such that the gate physically intercepts the outermost lateral portions of the beam, yet does not induce a significant electrostatic outward divergence of the beam, thereby reducing the cross-section of the beam.
摘要翻译：采用选择性蚀刻和化学机械平面化方法来形成围绕用于场发射显示器的电子发射尖端的自对准栅极和聚焦环结构。该方法用于构建发射栅极，由此栅极结构能够在阴极尖端产生足以产生电子发射的场强。门设置在尖端上方的位置，使得栅极物理地截取梁的最外侧部分，但不会引起梁的显着的静电向外发散，从而减小梁的横截面。

2. 发明授权

US5110754A Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM 失效
标题翻译：制造DRAM电容器的方法，用作用于DRAM上的冗余修复/选项的可编程反熔丝
公开(公告)号：US5110754A
公开(公告)日：1992-05-05
申请号：US771688
申请日：1991-10-04
申请人： Tyler A. Lowrey , Kevin G. Duesman , Eugene H. Cloud
发明人： Tyler A. Lowrey , Kevin G. Duesman , Eugene H. Cloud
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/525 , H01L27/118
CPC分类号： H01L27/10852 , H01L21/76888 , H01L23/5252 , H01L27/118 , H01L2924/0002
摘要： The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM's existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer's site.
摘要翻译：本发明涉及使用三维DRAM电容器作为一次性非易失性编程元件（可编程反熔丝）来进行冗余修复和/或在DRAM上选择其它选项的概念。本发明的可编程元件提供了一些显着的优点，例如较低的编程电压，其允许使用DRAM的现有操作电源，并且一旦完成编程，则仅需要一半的工作电压来测试元件。较低的编程电压允许在DRAM裸片封装之后进行的故障DRAM单元的冗余修复（或选择其他选项），包括在安装在客户现场之后。

3. 发明授权

US5324681A Method of making a 3-dimensional programmable antifuse for integrated circuits 失效
标题翻译：为集成电路制作3维可编程反熔丝的方法
公开(公告)号：US5324681A
公开(公告)日：1994-06-28
申请号：US22807
申请日：1993-02-22
申请人： Tyler A. Lowrey , Kevin G. Duesman , Eugene H. Cloud
发明人： Tyler A. Lowrey , Kevin G. Duesman , Eugene H. Cloud
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/525 , H01L27/118 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/76888 , H01L23/5252 , H01L27/118 , H01L2924/0002
摘要： The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM's existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer's site.
摘要翻译：本发明涉及使用三维DRAM电容器作为一次性非易失性编程元件（可编程反熔丝）来进行冗余修复和/或在DRAM上选择其它选项的概念。本发明的可编程元件提供了一些显着的优点，例如较低的编程电压，其允许使用DRAM的现有操作电源，并且一旦完成编程，则仅需要一半的工作电压来测试元件。较低的编程电压允许在DRAM裸片封装之后进行的故障DRAM单元的冗余修复（或选择其他选项），包括在安装在客户现场之后。

4. 发明授权

US5581159A Back-to-back diode current regulator for field emission display 失效
标题翻译：用于场发射显示的背对背二极管电流调节器
公开(公告)号：US5581159A
公开(公告)日：1996-12-03
申请号：US554853
申请日：1995-11-07
申请人： John K. Lee , Eugene H. Cloud , David A. Cathey, Jr.
发明人： John K. Lee , Eugene H. Cloud , David A. Cathey, Jr.
IPC分类号： G09G3/00 , G09G3/20 , G09G3/22 , H01J31/12 , H05B41/36 , H01J17/36
CPC分类号： G09G3/006 , G09G3/22 , H01J31/127 , G09G2300/0809 , G09G2310/0248 , G09G3/2011 , G09G3/2014 , H01J2201/319 , Y10S315/07
摘要： A circuit for regulating the pixel current in a field emission display so as to enhance pixel-to-pixel uniformity of pixel current. The pixel current flows through a pair of diodes connected back-to-back. A transistor circuit controls the voltage across the back-to-back diode pair, so that the voltage/current transfer characteristic of the diode pair determines the pixel current.
摘要翻译：用于调节场发射显示器中的像素电流以增强像素电流的像素到像素均匀性的电路。像素电流流过一对背对背连接的二极管。晶体管电路控制背对背二极管对上的电压，使得二极管对的电压/电流传递特性确定像素电流。

5. 发明授权

US07567091B2 Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
标题翻译：用于从半导体晶片上的其它IC隔离短路集成电路（IC）的方法
公开(公告)号：US07567091B2
公开(公告)日：2009-07-28
申请号：US12017262
申请日：2008-01-21
申请人： Warren M. Farnworth , William K. Waller , Leland R. Nevill , Raymond J. Beffa , Eugene H. Cloud
发明人： Warren M. Farnworth , William K. Waller , Leland R. Nevill , Raymond J. Beffa , Eugene H. Cloud
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01R31/2884
摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
摘要翻译：用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路电路。控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

6. 发明授权

US07129457B2 Redundant imaging systems 有权
标题翻译：冗余成像系统
公开(公告)号：US07129457B2
公开(公告)日：2006-10-31
申请号：US10868131
申请日：2004-06-15
申请人： David J. McElroy , Eugene H. Cloud
发明人： David J. McElroy , Eugene H. Cloud
IPC分类号： H01L21/00 , H04N9/64
CPC分类号： H01L27/14603 , H01L27/14609 , H04N5/367
摘要： Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately converted into digital image signals for recording or viewing. One problem with conventional imaging arrays concerns faulty photodetectors, which produce erroneous image signals that ultimately degrade the quality of resulting images. Accordingly, the present inventors devised new imaging arrays including redundant photodetectors to compensate for faulty ones. One exemplary embodiment includes photodetectors that are substantially smaller than conventional photodetectors and that are arranged into two or more groups, with the photodetectors in each group coupled to produce a single group image signal. If the group image signal for a group falls below some threshold level indicative of a defective or malfunctioning photodetector, the group image signal is amplified to compensate for the loss.
摘要翻译：成像阵列通常包括数千或数百万光电检测器，其将感测的光转换成对应的电信号，其最终被转换成用于记录或观看的数字图像信号。常规成像阵列的一个问题涉及故障光电探测器，其产生最终降低所得图像质量的错误图像信号。因此，本发明人设计了包括冗余光电检测器的新的成像阵列以补偿有缺陷的光检测器。一个示例性实施例包括基本上小于常规光电探测器并且被布置成两组或更多组的光电检测器，每组中的光电检测器耦合以产生单组图像信号。如果组的组图像信号低于指示有缺陷或故障的光电检测器的某个阈值电平，则对组图像信号进行放大以补偿损耗。

7. 发明授权

US07084351B2 Electrical device allowing for increased device densities 失效
公开(公告)号：US07084351B2
公开(公告)日：2006-08-01
申请号：US10237645
申请日：2002-09-09
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , J. Michael Brooks , Eugene H. Cloud
IPC分类号： H05K1/18
CPC分类号： H05K3/4007 , H01L23/4951 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K1/095 , H05K3/321 , H05K3/325 , H05K3/326 , H05K2201/0133 , H05K2201/0314 , H05K2201/0367 , H05K2201/09909 , H05K2201/10454 , H05K2201/10696 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate.

8. 发明授权

US06862662B1 High density storage scheme for semiconductor memory 失效
标题翻译：半导体存储器的高密度存储方案
公开(公告)号：US06862662B1
公开(公告)日：2005-03-01
申请号：US09518338
申请日：2000-03-03
申请人： Eugene H. Cloud
发明人： Eugene H. Cloud
IPC分类号： G06F11/10 , G06F12/08 , G11C7/10 , G06F12/00
CPC分类号： G06F11/1008 , G06F12/0893 , G06F2211/109 , G06F2212/3042 , G06F2212/401 , G11C7/1006
摘要： A memory device comprising a compression and decompression engine and a error detection and correction engine connected between a cache memory and a main memory in the same semiconductor chip.
摘要翻译：存储器件包括压缩和解压缩引擎以及连接在同一半导体芯片中的高速缓冲存储器和主存储器之间的错误检测和校正引擎。

9. 发明授权

US06741519B2 DRAM technology compatible processor/memory chips 有权
标题翻译： DRAM技术兼容处理器/内存芯片
公开(公告)号：US06741519B2
公开(公告)日：2004-05-25
申请号：US10191329
申请日：2002-07-09
申请人： Leonard Forbes , Eugene H. Cloud , Wendell P. Noble
发明人： Leonard Forbes , Eugene H. Cloud , Wendell P. Noble
IPC分类号： G11C800
CPC分类号： G11C7/1006 , G11C16/0416 , G11C16/08 , H01L27/1052 , H01L27/10852 , H01L27/10894 , H01L29/66825 , H03K19/17716
摘要： The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.
摘要翻译：本发明包括具有接收多个输入信号的第一逻辑平面的可编程逻辑阵列。第一逻辑平面具有互连以提供多个逻辑输出的以行和列布置的多个非易失性存储器单元。布置在第二逻辑平面的行和列中的多个非易失性存储单元接收第一逻辑平面的输出并互连以产生多个逻辑输出，使得可编程逻辑阵列实现逻辑功能。每个非易失性存储单元包括MOSFET。每个非易失性存储单元包括根据DRAM工艺形成的堆叠电容器。每个非易失性存储单元包括将堆叠的电容器耦合到MOSFET的栅极的电接触。本发明还包括用于制造IC和阵列的方法。

10. 发明授权

US06700821B2 Programmable mosfet technology and programmable address decode and correction 有权
标题翻译：可编程mosfet技术和可编程地址解码和校正
公开(公告)号：US06700821B2
公开(公告)日：2004-03-02
申请号：US09924659
申请日：2001-08-08
申请人： Leonard Forbes , Wendell P. Noble , Eugene H. Cloud
发明人： Leonard Forbes , Wendell P. Noble , Eugene H. Cloud
IPC分类号： G11C1604
CPC分类号： G11C29/789 , G11C8/08 , G11C8/10 , G11C11/4087 , G11C16/0466 , H01L27/10897 , H01L27/11803 , H03K3/356008
摘要： Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circuits in a DRAM integrated circuit. The structures and methods use the existing process sequence for MOSFET's in DRAM technology. In particular, an illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). In another embodiment of the present invention, the relatively small change in the programmed MOSFET of the novel circuit switch, in comparison to flash or EEPROM devices, is compensated for by using the novel circuit switch in a cross coupled latch. Methods, integrated circuits, and electronic systems are similarly provided and included within the scope of the present invention.
摘要翻译：根据DRAM优化的处理流程，针对DRAM芯片的PLA能力的结构和方法由本发明提供。这些结构和方法包括在DRAM集成电路中的存储器地址解码电路中使用MOSFET器件作为可再编程元件。结构和方法使用DRAM技术中的MOSFET的现有工艺顺序。特别地，本发明的说明性实施例包括非易失性可再编程电路开关。电路开关包括在衬底中的金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET具有源极区域，漏极区域，源极和漏极区域之间的沟道区域以及通过栅极氧化物与沟道区域分离的栅极。根据本发明的教导，MOSFET是编程的MOSFET，其具有与源极区相邻的栅极氧化物中的电荷，使得沟道区具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2 ）。在本发明的另一个实施例中，与闪存或EEPROM器件相比，新型电路开关的编程MOSFET的相对小的变化通过在交叉耦合的锁存器中使用新颖的电路开关来补偿。类似地提供了方法，集成电路和电子系统，并且包括在本发明的范围内。

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