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91. 发明授权

US08595443B2 Varying a data prefetch size based upon data usage 有权
标题翻译：基于数据使用改变数据预取大小
公开(公告)号：US08595443B2
公开(公告)日：2013-11-26
申请号：US12024163
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译：一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。基于使用历史来选择由数据预取请求预取的数据量。将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。

92. 发明授权

US08429349B2 Techniques for cache injection in a processor system with replacement policy position modification 失效
标题翻译：在具有替换政策位置修改的处理器系统中缓存注入的技术
公开(公告)号：US08429349B2
公开(公告)日：2013-04-23
申请号：US12212977
申请日：2008-09-18
申请人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana Baba Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0835 , G06F12/127 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).
摘要翻译：用于执行高速缓存注入的技术包括在缓存上监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。然后修改数据块的替换策略位置（以增加数据块在从高速缓存弹出之前消耗的概率）。

93. 发明授权

US08407680B2 Operand data structure for block computation 有权
标题翻译：块计算的操作数数据结构
公开(公告)号：US08407680B2
公开(公告)日：2013-03-26
申请号：US12336301
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F9/45
CPC分类号： G06F8/4441 , G06F8/447
摘要： In response to receiving pre-processed code, a compiler identifies a code section that is not a candidate for acceleration and a code block that is a candidate for acceleration. The code block specifies an iterated operation having a first operand and a second operand, where each of multiple first operands and each of multiple second operands for the iterated operation has a defined addressing relationship. In response to the identifying, the compiler generates post-processed code containing lower level instruction(s) corresponding to the identified code section and creates and outputs an operand data structure separate from the post-processed code. The operand data structure specifies the defined addressing relationship for the multiple first operands and for the multiple second operands. The compiler places a block computation command in the post-processed code that invokes processing of the operand data structure to compute operand addresses.
摘要翻译：响应于接收预处理的代码，编译器识别不是加速候选的代码段和作为加速候选的代码块。代码块指定具有第一操作数和第二操作数的迭代操作，其中用于迭代操作的多个第一操作数和多个第二操作数中的每一个具有定义的寻址关系。响应于识别，编译器生成包含对应于所识别的代码段的较低级别指令的后处理代码，并创建并输出与后处理代码分离的操作数数据结构。操作数数据结构指定多个第一个操作数和多个第二个操作数的定义的寻址关系。编译器在后处理代码中放置块计算命令，该代码调用操作数数据结构的处理以计算操作数地址。

94. 发明授权

US08327345B2 Computation table for block computation 有权
标题翻译：块计算的计算表
公开(公告)号：US08327345B2
公开(公告)日：2012-12-04
申请号：US12336332
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： In response to receiving pre-processed code, a compiler identifies a code section that is not candidate for acceleration and identifying a code block specifying an iterated operation that is a candidate for acceleration. In response to identifying the code section, the compiler generates post-processed code containing one or more lower level instructions corresponding to the identified code section, and in response to identifying the code block, the compiler creates and outputs an operation data structure separate from the post-processed code that identifies the iterated operation. The compiler places a block computation command in the post-processed code that invokes processing of the operation data structure to perform the iterated operation and outputs the post-processed code.
摘要翻译：响应于接收预处理的代码，编译器识别不是加速候选的代码段，并且识别指定作为加速候选的迭代操作的代码块。响应于识别代码部分，编译器生成包含与识别的代码部分相对应的一个或多个较低级别指令的后处理代码，并且响应于识别代码块，编译器创建并输出与标识迭代操作的后处理代码。编译器在后处理代码中放置块计算命令，该代码调用操作数据结构的处理以执行迭代操作，并输出后处理代码。

95. 发明授权

US08275963B2 Asynchronous memory move across physical nodes with dual-sided communication 有权
标题翻译：异步存储器通过双面通信跨物理节点移动
公开(公告)号：US08275963B2
公开(公告)日：2012-09-25
申请号：US12024486
申请日：2008-02-01
申请人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
发明人： Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Balaram Sinharoy , Hanhong Xue
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0811 , G06F12/084 , G06F12/0862
摘要： A distributed data processing system includes: (1) a first node with a processor, a first memory, and asynchronous memory mover logic; and connection mechanism that connects (2) a second node having a second memory. The processor includes processing logic for completing a cross-node asynchronous memory move (AMM) operation, wherein the processor performs a move of data in virtual address space from a first effective address to a second effective address, and the asynchronous memory mover logic completes a physical move of the data from a first memory location in the first memory having a first real address to a second memory location in the second memory having a second real address. The data is transmitted via the connection mechanism connecting the two nodes independent of the processor.
摘要翻译：分布式数据处理系统包括：（1）具有处理器的第一节点，第一存储器和异步存储器移动器逻辑; 以及连接机构，其连接（2）具有第二存储器的第二节点。处理器包括用于完成跨节点异步存储器移动（AMM）操作的处理逻辑，其中处理器执行将虚拟地址空间中的数据从第一有效地址移动到第二有效地址，并且异步存储器移动器逻辑完成从具有第一实际地址的第一存储器中的第一存储器位置的数据的物理移动到具有第二实际地址的第二存储器中的第二存储器位置。数据通过连接独立于处理器的两个节点的连接机制进行传输。

96. 发明授权

US08176254B2 Specifying an access hint for prefetching limited use data in a cache hierarchy 失效
标题翻译：指定在缓存层次结构中预取有限使用数据的访问提示
公开(公告)号：US08176254B2
公开(公告)日：2012-05-08
申请号：US12424681
申请日：2009-04-16
申请人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
发明人： Bradly G. Frey , Guy L. Guthrie , Cathy May , Balaram Sinharoy , Peter K. Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache.
摘要翻译：一种用于指定预取有限使用数据的访问提示的系统和方法。处理单元接收具有指示给处理单元的访问提示的数据高速缓存块触摸（DCBT）指令，即在数据处理系统上执行的程序可以很快访问在DCBT指令内寻址的高速缓存块。访问提示包含在存储在DCBT指令的子字段中的代码点中。响应于检测到代码点被设置为特定值，DCBT指令中寻址的数据被预取到低级缓存中的条目中。然后可以将条目作为较低级别高速缓存中的多个条目的最近最少使用的条目来更新。响应于将新的高速缓存块提取到高速缓存，预取的高速缓存块被抛出高速缓存。

97. 发明授权

US08145885B2 Apparatus for randomizing instruction thread interleaving in a multi-thread processor 有权
标题翻译：用于在多线程处理器中随机化指令线程交错的装置
公开(公告)号：US08145885B2
公开(公告)日：2012-03-27
申请号：US12112859
申请日：2008-04-30
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/3851
摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.
摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。根据规则选择每个线程的频率可以基于分配给指令线程的优先级。随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。

98. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

99. 发明授权

US08127115B2 Group formation with multiple taken branches per group 失效
标题翻译：每组多组分组成组
公开(公告)号：US08127115B2
公开(公告)日：2012-02-28
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译：公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。

100. 发明授权

US08086826B2 Dependency tracking for enabling successive processor instructions to issue 有权
标题翻译：用于启用连续处理器指令发布的依赖性跟踪
公开(公告)号：US08086826B2
公开(公告)日：2011-12-27
申请号：US12409934
申请日：2009-03-24
申请人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
发明人： Mary Douglass Brown , William Elton Burky , Dung Quoc Nguyen , Balaram Sinharoy
IPC分类号： G06F9/38 , G06F9/52
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions along with relative instruction to instruction dependency information. A mapper maps queue position data for instructions that dispatch to issue queue locations within the IU. The IU may test an issuing producer instruction against consumer instructions in the IU for queue position (QPOS) and register tag (RTAG) matches. A matching consumer instruction may issue in a successive manner in the case of a queue position match or in a next processor cycle in the case of a register tag match.
摘要翻译：信息处理系统包括具有发布单元（IU）的处理器，该单元可对连续指令发布操作执行指令依赖性跟踪。 IU保持非移位问题队列（NSIQ）和移位发送队列（SIQ）指令以及与指令依赖信息的相关指令。映射器映射队列位置数据，用于发送在IU内发出队列位置的指令。 IU可以根据IU中的消费者指令测试发出生产者指令的队列位置（QPOS）和注册标签（RTAG）匹配。在队列位置匹配的情况下，或者在注册标签匹配的情况下，在下一个处理器周期中，匹配的消费者指令可以以连续的方式发布。

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