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1. 发明申请

US20080209426A1 APPARATUS FOR RANDOMIZING INSTRUCTION THREAD INTERLEAVING IN A MULTI-THREAD PROCESSOR 有权
标题翻译：用于在多线程处理器中指示线程交叉的随机设备
公开(公告)号：US20080209426A1
公开(公告)日：2008-08-28
申请号：US12112859
申请日：2008-04-30
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Ballarm Sinharoy , John Wesley Ward, III
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Ballarm Sinharoy , John Wesley Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/3851
摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.
摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。根据规则选择每个线程的频率可以基于分配给指令线程的优先级。随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。

2. 发明授权

US08145885B2 Apparatus for randomizing instruction thread interleaving in a multi-thread processor 有权
标题翻译：用于在多线程处理器中随机化指令线程交错的装置
公开(公告)号：US08145885B2
公开(公告)日：2012-03-27
申请号：US12112859
申请日：2008-04-30
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/3851
摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.
摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。根据规则选择每个线程的频率可以基于分配给指令线程的优先级。随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。

3. 发明授权

US07827388B2 Apparatus for adjusting instruction thread priority in a multi-thread processor 有权
标题翻译：用于在多线程处理器中调整指令线程优先级的装置
公开(公告)号：US07827388B2
公开(公告)日：2010-11-02
申请号：US12044846
申请日：2008-03-07
申请人： John Wesley Ward, III , Minh Michelle Quy Pham , Ronald Nick Kalla , Balaram Sinharoy
发明人： John Wesley Ward, III , Minh Michelle Quy Pham , Ronald Nick Kalla , Balaram Sinharoy
IPC分类号： G06F9/40 , G06F9/42
CPC分类号： G06F9/4818 , G06F9/3851
摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。

4. 发明授权

US07401207B2 Apparatus and method for adjusting instruction thread priority in a multi-thread processor 有权
标题翻译：用于调整多线程处理器中指令线程优先级的装置和方法
公开(公告)号：US07401207B2
公开(公告)日：2008-07-15
申请号：US10424529
申请日：2003-04-25
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
IPC分类号： G06F9/40 , G06F9/44
CPC分类号： G06F9/4818 , G06F9/3851
摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。

5. 发明申请

US20080162904A1 APPARATUS FOR SELECTING AN INSTRUCTION THREAD FOR PROCESSING IN A MULTI-THREAD PROCESSOR 审中-公开
标题翻译：选择用于多线程处理器处理的指令螺纹的装置
公开(公告)号：US20080162904A1
公开(公告)日：2008-07-03
申请号：US12048171
申请日：2008-03-13
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward
IPC分类号： G06F9/38
CPC分类号： G06F9/3851
摘要： The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.
摘要翻译：可以修改SMT处理器中用于交织来自不同指令线程的指令的指令线程之间的选择以适应某些处理器事件或条件。在每个处理器时钟周期期间，交错规则实施部件产生至少一个基本指令线程选择信号，其指示用于将指令从该特定线程传递到交错指令流中的特定指令线程。线程选择修改由交织修改组件提供，交织修改组件基于基本线程选择信号和从各种处理器元件中的一个或多个条件或事件导出的反馈信号生成最后的线程选择信号。该最终线程选择信号可以指示由基线程选择信号指示的相同指令线程或用于将指令传递到交错指令流的指令线程中的不同指令线程。

6. 发明申请

US20080155233A1 APPARATUS FOR ADJUSTING INSTRUCTION THREAD PRIORITY IN A MULTI-THREAD PROCESSOR 有权
标题翻译：用于调整多线程处理器中的指令优先级的设备
公开(公告)号：US20080155233A1
公开(公告)日：2008-06-26
申请号：US12044846
申请日：2008-03-07
申请人： John Wesley Ward , Minh Michelle Quy Pham , Ronald Nick Kalla , Balaram Sinharoy
发明人： John Wesley Ward , Minh Michelle Quy Pham , Ronald Nick Kalla , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/4818 , G06F9/3851
摘要： Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
摘要翻译： SMT处理器中的每个指令线程与软件分配的基本输入处理优先级相关联。除非正在处理或要处理的指令发生一些预定义的事件或情况，否则各个线程的基本输入处理优先级用于根据某种指令交错规则来确定线程之间的交织频率。然而，在与特定指令线程相关的处理器中发生某些预定义的事件或环境时，调整一个或多个指令线程的基本输入处理优先级以产生一个更多调整的优先级值。然后根据调整后的优先级值或与未经调整的任何基本输入处理优先级值一起实施指令交错规则。

7. 发明授权

US07401208B2 Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor 有权
标题翻译：在多线程处理器中随机化指令线程交错的方法和装置
公开(公告)号：US07401208B2
公开(公告)日：2008-07-15
申请号：US10424533
申请日：2003-04-25
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/3851
摘要： A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.
摘要翻译： A处理器根据优先级规则对指令进行交织，该优先级规则确定选择来自每个相应线程的指令的频率，并将其附加到要在数据处理器中处理的交错指令流。根据规则选择每个线程的频率可以基于分配给指令线程的优先级。随机化被插入到交织处理中，使得在任何特定时钟周期期间指令线程的选择不仅仅基于优先级规则，而且还部分地基于随机或伪随机元素。该随机化被插入到指令线程选择处理中，以便改变从各种指令线程中选择指令的顺序，同时保持由优先级规则设置的线程选择的总体频率（即选择多少线程）。

8. 发明授权

US07360062B2 Method and apparatus for selecting an instruction thread for processing in a multi-thread processor 失效
标题翻译：一种用于在多线程处理器中选择用于处理的指令线程的方法和装置
公开(公告)号：US07360062B2
公开(公告)日：2008-04-15
申请号：US10424530
申请日：2003-04-25
申请人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
发明人： Ronald Nick Kalla , Minh Michelle Quy Pham , Balaram Sinharoy , John Wesley Ward, III
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/46
CPC分类号： G06F9/3851
摘要： The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.
摘要翻译：可以修改SMT处理器中用于交织来自不同指令线程的指令的指令线程之间的选择以适应某些处理器事件或条件。在每个处理器时钟周期期间，交错规则实施部件产生至少一个基本指令线程选择信号，其指示用于将指令从该特定线程传递到交错指令流中的特定指令线程。线程选择修改由交织修改组件提供，交织修改组件基于基本线程选择信号和从各种处理器元件中的一个或多个条件或事件导出的反馈信号生成最后的线程选择信号。该最终线程选择信号可以指示由基线程选择信号指示的相同指令线程或用于将指令传递到交错指令流的指令线程中的不同指令线程。

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