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1. 发明公开

US20240028523A1 ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM 审中-公开
公开(公告)号：US20240028523A1
公开(公告)日：2024-01-25
申请号：US18477674
申请日：2023-09-29
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Naveen Bhoria , Timothy David Anderson , Pete Michael Hippleheuser
IPC分类号： G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126 , G06F12/127
CPC分类号： G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/546 , G06F12/0215 , G06F12/0238 , G06F12/0811 , G06F12/082 , G06F12/0804 , G06F9/3001 , G06F9/30047 , G11C7/106 , G11C7/1087 , G11C29/42 , G11C29/44 , G06F11/1064 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/1605 , G06F12/121 , G06F12/0292 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/222 , G11C7/1075 , G11C7/1078 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G11C5/066 , G11C7/10 , G11C7/1015 , G06F15/8069 , G06F12/0802 , G06F9/30043 , G06F12/126 , G06F12/127 , G06F2212/1021 , G06F2212/608 , G06F2212/6032 , G06F2212/1024 , G06F2212/62 , G06F2212/1016 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6042
摘要： Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

2. 发明授权

US11762778B2 Efficient cache eviction and insertions for sustained steady state performance 有权
公开(公告)号：US11762778B2
公开(公告)日：2023-09-19
申请号：US17504490
申请日：2021-10-18
申请人： Samsung Electronics Co., Ltd.
发明人： Vijaya Kumar Jakkula , Siva Ramineni , Venkata Bhanu Prakash Gollapudi
IPC分类号： G06F12/0891 , G06F12/127 , G06F12/0817 , G06F9/50 , G06F9/30
CPC分类号： G06F12/0891 , G06F9/3009 , G06F9/5016 , G06F9/5022 , G06F12/0824 , G06F12/127 , G06F2209/5011 , G06F2209/5022 , G06F2212/1021 , G06F2212/7207
摘要： A distributed metadata cache for a distributed object store includes a plurality of cache entries, an active-cache-entry set and an unreferenced-cache-entry set. Each cache entry includes information relating to whether at least one input/output (IO) thread is referencing the cache entry and information relating to whether the cache entry is no longer referenced by at least one IO thread. Each cache entry in the active-cache-entry set includes information that indicates that at least one IO thread is actively referencing the cache entry. Each cache entry in the unreferenced-cache-entry set is eligible for eviction from the distributed metadata cache by including information that indicates that the cache entry is no longer actively referenced by an IO thread.

3. 发明授权

US10037271B1 Data-temperature-based control of buffer cache memory in a database system 有权
公开(公告)号：US10037271B1
公开(公告)日：2018-07-31
申请号：US13535323
申请日：2012-06-27
申请人： Brian M. Andersen
发明人： Brian M. Andersen
IPC分类号： G06F17/00 , G06F12/08 , G06F12/0808 , G06F12/0815 , G06F12/02
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/0656 , G06F3/0688 , G06F3/0689 , G06F12/0868 , G06F12/122 , G06F12/123 , G06F12/127 , G06F12/128 , G06F16/24552 , G06F2212/1016 , G06F2212/163 , G06F2212/2515 , G06F2212/261
摘要： A database system may include a memory device that includes a least a portion to serve as a buffer cache and an array of persistent storage devices configured to store data of a database. The database system may monitor a frequency of data value associated with a first portion of data of the database stored in the buffer cache. The database system may maintain the first portion of data in the buffer cache in response to the frequency of data value associated with the first portion of data being greater than a frequency of data value associated with at least a portion of the data of the database stored in the array of persistent storage devices.

4. 发明申请

US20180173636A1 INCREASING LIFETIME RELIABILITY FOR A CACHE MEMORY 审中-公开
公开(公告)号：US20180173636A1
公开(公告)日：2018-06-21
申请号：US15385604
申请日：2016-12-20
申请人： Intel Corporation
发明人： Elizabeth Reed , Alaa R. Alameldeen , Helia Naeimi , Patrick F. Stolt
IPC分类号： G06F12/0891
CPC分类号： G06F12/0891 , G06F12/123 , G06F12/127 , G06F2212/1036 , G06F2212/60
摘要： A first request to evict a first cache line that is stored in a cache memory may be received. The first cache line may be evicted based on a replacement policy. A second request to evict a second cache line from the cache memory may be received. Following the receipt of the second request, it is determined whether a condition associated with the replacement policy has been satisfied. If the condition associated with replacement policy has been satisfied, then the second cache line may be evicted based on a random replacement policy.

5. 发明授权

US09921963B1 Method to decrease computation for cache eviction using deferred calculations 有权
公开(公告)号：US09921963B1
公开(公告)日：2018-03-20
申请号：US14609928
申请日：2015-01-30
申请人： EMC Corporation
发明人： Cheng Li , Philip Shilane , Grant Wallace
IPC分类号： G06F12/08 , G06F12/12 , G06F12/0831 , G06F12/122 , G06F12/123
CPC分类号： G06F12/0833 , G06F12/12 , G06F12/122 , G06F12/123 , G06F12/127 , G06F2212/62 , G06F2212/7207
摘要： A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of a cache device, wherein the cache device comprises a plurality of cache units, each cache unit having a plurality of segments, calculating a score for each metadata set, and arranging the metadata sets in a list in ascending order from lowest score to highest score. The exemplary method further includes in response to determining that a cache eviction is to be performed, selecting a cache unit corresponding to the metadata set in the list having the lowest score, without recalculating a score for any of the metadata set, and evicting the selected cache unit. The metadata nay include, for example, segment count metadata, validity metadata, last access time (LAT) metadata, and hotness metadata.

6. 发明授权

US09811468B2 Set associative cache memory with heterogeneous replacement policy 有权
公开(公告)号：US09811468B2
公开(公告)日：2017-11-07
申请号：US14890895
申请日：2014-12-14
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： Rodney E. Hooker , Douglas R. Reed , John Michael Greer , Colin Eddy
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/0864 , G06F12/128 , G06F12/127 , G06F9/45 , G06F12/0846
CPC分类号： G06F12/0864 , G06F8/4442 , G06F12/0846 , G06F12/127 , G06F12/128 , G06F2212/1021 , G06F2212/6032 , G06F2212/6082 , Y02D10/13
摘要： A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set; for each parcel of a plurality of parcels, a parcel specifier specifies: a subset of ways of the N ways included in the parcel. The subsets of ways of parcels associated with a selected set are mutually exclusive; a replacement scheme associated with the parcel from among a plurality of predetermined replacement schemes. For each memory access, the allocation unit: selects the parcel specifier in response to the memory access; and uses the replacement scheme associated with the parcel to allocate into the subset of ways of the selected set included in the parcel.

7. 发明申请

US20170242624A1 APPARATUS AND METHOD FOR OPTIMIZED N-WRITE/1-READ PORT MEMORY DESIGN 有权
公开(公告)号：US20170242624A1
公开(公告)日：2017-08-24
申请号：US15047987
申请日：2016-02-19
申请人： CAVIUM, INC.
发明人： Saurin Patel , Weihuang Wang
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/067 , G06F3/0683 , G06F12/0223 , G06F12/06 , G06F12/0623 , G06F12/0802 , G06F12/0846 , G06F12/0857 , G06F12/127 , G06F13/4256 , G06F13/4273 , G06F13/4291 , G06F2212/1048 , H04L49/00
摘要： An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

8. 发明申请

US20170083455A1 CACHE ACCESS STATISTICS ACCUMULATION FOR CACHE LINE REPLACEMENT SELECTION 有权
公开(公告)号：US20170083455A1
公开(公告)日：2017-03-23
申请号：US14861055
申请日：2015-09-22
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Philip J. Rogers , Benjamin T. Sander , Anthony Asaro
IPC分类号： G06F12/12 , G06F12/10 , G06F13/28 , G06F12/08
CPC分类号： G06F12/121 , G06F12/0891 , G06F12/0895 , G06F12/1081 , G06F12/12 , G06F12/127 , G06F13/28 , G06F2212/656
摘要： A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.

9. 发明授权

US09569367B1 Cache eviction based on types of data stored in storage systems 有权
标题翻译：基于存储在存储系统中的数据类型的缓存驱逐
公开(公告)号：US09569367B1
公开(公告)日：2017-02-14
申请号：US14196308
申请日：2014-03-04
申请人： EMC Corporation
发明人： Ian Wigmore , Marik Marshak , Arieh Don , Alexandr Veprinsky
IPC分类号： G06F12/08 , G06F12/12 , G06F11/14
CPC分类号： G06F12/0891 , G06F11/1448 , G06F11/1461 , G06F12/0804 , G06F12/0868 , G06F12/0897 , G06F12/121 , G06F12/123 , G06F12/126 , G06F12/127 , G06F2212/1016 , G06F2212/1044 , G06F2212/463
摘要： Exemplary methods for improving cache utilization include in response to receiving a request to store data, storing the data in one of a plurality of cache slots of a cache. In one embodiment, the methods further include after storing the data, setting a status of the cache slot as write pending to indicate that the cache slot contains data which needs to be written to a corresponding destination storage device. The methods include determining an eviction type of the cached data based on whether the destination storage device is a local storage device or a remote storage device. In one embodiment, after copying data from the cache slot to the corresponding destination storage device, marking the cache slot with the determined eviction type. In response to receiving another request to store data, evicting at least one of the cache slots based on the eviction type.
摘要翻译：用于提高高速缓存利用率的示例性方法包括响应于接收到存储数据的请求，将数据存储在高速缓存的多个高速缓存时隙之一中。在一个实施例中，所述方法还包括在存储数据之后，将高速缓存时隙的状态设置为等待写入，以指示高速缓存时隙包含需要写入相应目的地存储设备的数据。所述方法包括基于目的地存储设备是本地存储设备还是远程存储设备来确定缓存数据的逐出类型。在一个实施例中，在将数据从高速缓存时隙复制到相应的目的地存储设备之后，用所确定的驱逐类型标记高速缓存时隙。响应于接收另一个存储数据的请求，基于驱逐类型来驱逐高速缓存槽中的至少一个。

10. 发明授权

US09535837B2 Decentralized online cache management for digital content conveyed over shared network connections based on cache fullness and cache eviction policies 有权
标题翻译：基于缓存充满度和缓存驱逐策略，通过共享网络连接传输的数字内容的分散式在线缓存管理
公开(公告)号：US09535837B2
公开(公告)日：2017-01-03
申请号：US14083723
申请日：2013-11-19
申请人： ALCATEL-LUCENT USA INC.
发明人： Mohammadali Maddah-Ali , Urs Niesen , Ramtin Pedarsani
IPC分类号： G06F13/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0813 , G06F12/123 , G06F12/127 , G06F2212/1016
摘要： A first cache is provided to cache a first portion of a first block of digital content received over a network connection shared between a first user associated with the first cache and at least one second user. The first cache caches the first portion in response to the first user or the second user(s) requesting the first block. The first cache selects the first portion based on a fullness of the first cache, a number of blocks cached in the first cache, or a cache eviction rule associated with the first cache.
摘要翻译：提供第一缓存以缓存通过在与第一高速缓存相关联的第一用户与至少一个第二用户之间共享的网络连接上接收的第一数字内容块的第一部分。第一缓存响应于请求第一块的第一用户或第二用户缓存第一部分。第一缓存基于第一高速缓存的充满度，缓存在第一高速缓存中的块的数量或与第一高速缓存相关联的高速缓存驱逐规则来选择第一部分。

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