专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08266381B2 Varying an amount of data retrieved from memory based upon an instruction hint 失效
标题翻译：根据指令提示改变从存储器检索的数据量
公开(公告)号：US08266381B2
公开(公告)日：2012-09-11
申请号：US12024170
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0822 , G06F2212/507 , G06F2212/6028
摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
摘要翻译：在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

2. 发明申请

US20090198965A1 METHOD AND SYSTEM FOR SOURCING DIFFERING AMOUNTS OF PREFETCH DATA IN RESPONSE TO DATA PREFETCH REQUESTS 失效
标题翻译：用于根据数据预先要求采集预取数据的不同数据的方法和系统
公开(公告)号：US20090198965A1
公开(公告)日：2009-08-06
申请号：US12024165
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3455
摘要： According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.
摘要翻译：根据数据处理的方法，存储器控制器从数据处理系统的处理器核心接收预取负载请求。预取加载请求指定所请求的数据行。响应于接收到预取加载请求，存储器控制器通过参考需求请求流来确定响应于预取加载请求将多少数据提供给处理器核。响应于存储器控制器确定提供少于全部所请求的数据行，存储器控制器将少于所有请求的数据行提供给处理器核。

3. 发明申请

US20100293339A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR VARYING A DATA PREFETCH SIZE BASED UPON DATA USAGE 有权
标题翻译：数据处理系统，用于根据数据使用改变数据预设尺寸的处理器和方法
公开(公告)号：US20100293339A1
公开(公告)日：2010-11-18
申请号：US12024163
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译：一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。基于使用历史来选择由数据预取请求预取的数据量。将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。

4. 发明申请

US20090198910A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA 审中-公开
标题翻译：数据处理系统，处理器和方法，支持部分缓存行数据
公开(公告)号：US20090198910A1
公开(公告)日：2009-08-06
申请号：US12024174
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831
摘要： According to method of data processing in a multiprocessor data processing system, in response to a processor touch request targeting a target granule of a cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial touch request that requests a copy of only the target granule for subsequent query access. In response to a combined response to the partial touch request indicating success, the combined response representing a system-wide response to the partial touch request, the processing unit receives the target granule of the target cache line and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the cache line.
摘要翻译：根据多处理器数据处理系统中的数据处理方法，响应于针对包含多个粒子的数据的高速缓存行的目标颗粒的处理器触摸请求，处理单元起源于多处理器数据处理系统的互连部分触摸请求仅请求目标颗粒的副本用于后续查询访问。响应于指示成功的部分触摸请求的组合响应，表示对部分触摸请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒并更新目标颗粒的一致性状态同时保持高速缓存行的至少另一个颗粒的一致性状态。

5. 发明授权

US08250307B2 Sourcing differing amounts of prefetch data in response to data prefetch requests 失效
标题翻译：根据数据预取请求采购不同数量的预取数据
公开(公告)号：US08250307B2
公开(公告)日：2012-08-21
申请号：US12024165
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3455
摘要： According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.
摘要翻译：根据数据处理的方法，存储器控制器从数据处理系统的处理器核心接收预取负载请求。预取加载请求指定所请求的数据行。响应于接收到预取加载请求，存储器控制器通过参考需求请求流来确定响应于预取加载请求将多少数据提供给处理器核。响应于存储器控制器确定提供少于全部所请求的数据行，存储器控制器将少于所有请求的数据行提供给处理器核。

6. 发明申请

US20090198903A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT VARY AN AMOUNT OF DATA RETRIEVED FROM MEMORY BASED UPON A HINT 失效
标题翻译：数据处理系统，处理器和方法，从基于记忆的记忆中提取的数据量变化不大
公开(公告)号：US20090198903A1
公开(公告)日：2009-08-06
申请号：US12024170
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0822 , G06F2212/507 , G06F2212/6028
摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
摘要翻译：在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

7. 发明授权

US08595443B2 Varying a data prefetch size based upon data usage 有权
标题翻译：基于数据使用改变数据预取大小
公开(公告)号：US08595443B2
公开(公告)日：2013-11-26
申请号：US12024163
申请日：2008-02-01
申请人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： Ravi K. Arimilli , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译：一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。基于使用历史来选择由数据预取请求预取的数据量。将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。

8. 发明授权

US09798528B2 Software solution for cooperative memory-side and processor-side data prefetching 有权
公开(公告)号：US09798528B2
公开(公告)日：2017-10-24
申请号：US11531313
申请日：2006-09-13
申请人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
发明人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
IPC分类号： G06F9/45 , G06F12/0811 , G06F12/08 , G06F12/0862
CPC分类号： G06F8/4442 , G06F8/40 , G06F8/41 , G06F8/443 , G06F8/4441 , G06F12/08 , G06F12/0811 , G06F12/0862 , G06F2212/6028
摘要： A solution for cooperative data prefetching that enables software control of a memory-side data prefetch and/or a processor-side data prefetch is provided. In one embodiment, the invention provides a solution for generating an application, in which access to application data for the application is improved (e.g., optimized) in program code for the application. In particular, a push request, for performing a memory-side data prefetch of the application data, and a prefetch request, for performing a processor-side data prefetch, are added to the program code. The memory-side data prefetch results in the application data being copied from a first data store to a second data store that is faster than the first data store while the processor-side data prefetch results in the application data being copied from the second data store to a third data store that is faster than the second data store.

9. 发明申请

US20080127131A1 SOFTWARE SOLUTION FOR COOPERATIVE MEMORY-SIDE AND PROCESSOR-SIDE DATA PREFETCHING 有权
标题翻译：合作存储器和处理器数据预编译软件解决方案
公开(公告)号：US20080127131A1
公开(公告)日：2008-05-29
申请号：US11531313
申请日：2006-09-13
申请人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
发明人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
IPC分类号： G06F12/08 , G06F9/45
CPC分类号： G06F8/4442 , G06F8/40 , G06F8/41 , G06F8/443 , G06F8/4441 , G06F12/08 , G06F12/0811 , G06F12/0862 , G06F2212/6028
摘要： A solution for cooperative data prefetching that enables software control of a memory-side data prefetch and/or a processor-side data prefetch is provided. In one embodiment, the invention provides a solution for generating an application, in which access to application data for the application is improved (e.g., optimized) in program code for the application. In particular, a push request, for performing a memory-side data prefetch of the application data, and a prefetch request, for performing a processor-side data prefetch, are added to the program code. The memory-side data prefetch results in the application data being copied from a first data store to a second data store that is faster than the first data store while the processor-side data prefetch results in the application data being copied from the second data store to a third data store that is faster than the second data store.
摘要翻译：提供了一种用于协同数据预取的解决方案，其实现对存储器侧数据预取和/或处理器侧数据预取的软件控制。在一个实施例中，本发明提供了一种用于生成应用的解决方案，其中在应用的程序代码中改进（例如，优化）应用程序的应用数据的访问。特别地，用于执行应用数据的存储器侧数据预取的推送请求和用于执行处理器侧数据预取的预取请求被添加到程序代码。存储器侧数据预取导致应用数据从第一数据存储器复制到比第一数据存储器更快的第二数据存储器，而处理器侧数据预取导致应用数据从第二数据存储器复制到比第二数据存储更快的第三数据存储。

10. 发明授权

US08136103B2 Combining static and dynamic compilation to remove delinquent loads 有权
标题翻译：结合静态和动态编译来消除违规负载
公开(公告)号：US08136103B2
公开(公告)日：2012-03-13
申请号：US12058172
申请日：2008-03-28
申请人： Gheorghe C. Cascaval , Yaoqing Gao , Allan H. Kielstra , Kevin A. Stoodley
发明人： Gheorghe C. Cascaval , Yaoqing Gao , Allan H. Kielstra , Kevin A. Stoodley
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F12/0862
摘要： A method for combined static and dynamic compilation of program code to remove delinquent loads can include statically compiling source code into executable code with instrumented sections each being suspected of including a delinquent load, and also into a separate intermediate language representation with annotated portions each corresponding to one of the instrumented sections. The method also can include executing the instrumented sections repeatedly and monitoring cache misses for each execution. Finally, the method can include dynamically recompiling selected ones of the instrumented sections using corresponding ones of the annotated portions of the separate intermediate language representation only after a threshold number of executions of the selected ones of the instrumented sections, each recompilation include a pre-fetch directive at a pre-fetch distances tuned to avoid the delinquent load.
摘要翻译：用于组合静态和动态编译程序代码以消除违规负载的方法可以包括将源代码静态地编译成可执行代码，其中每个都被怀疑包含拖欠负载的检测部分，并且还包括具有注释部分的单独的中间语言表示，每个对应于其中一个仪器部分。该方法还可以包括重复执行检测的部分，并监视每次执行的高速缓存未命中。最后，该方法可以包括仅在所选择的被检测部分的阈值数量执行之后，使用单独的中间语言表示的对应注释部分中的对应的部分动态重新编译所选择的部分部分，每次重新编译包括预取指令以预取距离进行调整，以避免拖欠负荷。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式