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1. 发明授权

US07605612B1 Techniques for reducing power requirements of an integrated circuit 失效
标题翻译：降低集成电路功耗要求的技术
公开(公告)号：US07605612B1
公开(公告)日：2009-10-20
申请号：US12121827
申请日：2008-05-16
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Daniel L. Stasiak , Albert J. Van Norstrand, Jr.
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3237 , G06F17/505 , G06F2217/78 , G06F2217/84 , Y02D10/128
摘要： A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.
摘要翻译：时钟选通集成电路的时钟域的技术包括将第一，第二和第三值存储在控制寄存器中。第一值对应于在启动时钟门控之前等待的第一数量的时钟周期，第二值对应于执行时钟门控的第二数量的时钟周期，并且第三值对应于第三数量的时钟周期，其中不执行时钟门控。第一，第二和第三值之一被选择性地从控制寄存器加载到计数电路中。计数电路从加载的第一，第二和第三值之一计数到转换值。在控制状态机（从计数电路）接收到比较信号，指示计数电路已经达到转换值。基于控制状态机的当前状态，向计数电路提供负载信号，使得计数电路从控制寄存器加载相关的第一，第二和第三值中的一个。

2. 发明申请

US20090006817A1 Mechanisms for Placing a Processor into a Gradual Slow Mode of Operation 有权
标题翻译：将处理器置于逐渐缓慢运行模式的机制
公开(公告)号：US20090006817A1
公开(公告)日：2009-01-01
申请号：US12204865
申请日：2008-09-05
申请人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, JR.
发明人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/524
摘要： Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译：提供了将处理器置于逐渐减速操作模式的机制。逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。处理器逐渐减速使处理器能够突破活动锁定状态。此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

3. 发明授权

US5446913A Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array 失效
标题翻译：在使用完成指令数组的数据处理系统中不相继执行混合标量和向量指令的方法和系统
公开(公告)号：US5446913A
公开(公告)日：1995-08-29
申请号：US991665
申请日：1992-12-16
申请人： Norman C. Chou , Edward J. D'Avignon , James C. Gregerson , James R. Robinson , Michael S. Siegel , Michael A. Smoolca , Albert J. Van Norstrand, Jr.
发明人： Norman C. Chou , Edward J. D'Avignon , James C. Gregerson , James R. Robinson , Michael S. Siegel , Michael A. Smoolca , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/38 , G06F9/26 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3836
摘要： A method and system for enhancing processing efficiency in a data processing system which includes multiple scalar instruction processors and a vector instruction processor. An ordered sequence of intermixed scalar and vector instructions is processed in a nonsequential order by coupling those instructions to selected processors. As each instruction is finished an indication of that state is stored within a finish instruction array. The first vector instruction within the ordered sequence is initiated within the vector instruction processor only after an indication that each scalar instruction preceding the first vector instruction is finished. A vector advance signal is generated by the vector instruction processor each time processing of a vector instruction is initiated. A subsequent vector instruction is then initiated when the vector processor assets are available only in response to the presence of the vector advance signal and an indication that all scalar instructions which proceed the subsequent vector instruction within the ordered sequence have finished, without encountering an exception. In this manner, chained processing of vector instructions may be accomplished by initiating processing of a subsequent vector instruction only after possible interruption by a scalar instruction exception is no longer possible.
摘要翻译：一种用于提高包括多个标量指令处理器和向量指令处理器的数据处理系统中的处理效率的方法和系统。通过将这些指令耦合到所选择的处理器，以非顺序的顺序处理混合标量和向量指令的有序序列。当每个指令完成时，该状态的指示被存储在完成指令数组中。只有在第一个向量指令之前的每个标量指令完成的指示之后，才能在向量指令处理器内启动有序序列内的第一个向量指令。每次向量指令的处理开始时，矢量提前信号由矢量指令处理器产生。然后，当向量处理器资产仅在响应于向量提前信号的存在而可用时才启动随后的向量指令，并且指示在序列序列中进行随后的向量指令的所有标量指令已经完成，而不会遇到异常。以这种方式，可以通过仅在通过标量指令异常的可能中断之后启动对后续向量指令的处理来实现向量指令的链接处理。

4. 发明授权

US07818544B2 Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition 有权
标题翻译：处理器在锁定状态检测期间通过逐步停止指令处理速度来恢复恢复
公开(公告)号：US07818544B2
公开(公告)日：2010-10-19
申请号：US12204865
申请日：2008-09-05
申请人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
发明人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/28
CPC分类号： G06F9/524
摘要： Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译：提供了将处理器置于逐渐减速操作模式的机制。逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。处理器逐渐减速使处理器能够突破活动锁定状态。此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

5. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

6. 发明授权

US08200946B2 Issue unit for placing a processor into a gradual slow mode of operation 有权
标题翻译：用于将处理器置于逐渐缓慢运行模式的发行单元
公开(公告)号：US08200946B2
公开(公告)日：2012-06-12
申请号：US12207545
申请日：2008-09-10
申请人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
发明人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30181 , G06F9/30189 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3861
摘要： An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译：提供了一种用于将处理器置于逐渐减速操作模式的问题单元。逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。处理器逐渐减速使处理器能够突破活动锁定状态。此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

7. 发明申请

US20100262806A1 Tracking Effective Addresses in an Out-of-Order Processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US20100262806A1
公开(公告)日：2010-10-14
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

8. 发明授权

US07437539B2 Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline 有权
标题翻译：发送单元，用于响应于处理器流水线内检测到的活动锁定状态，将处理器置于逐渐缓慢的操作模式中
公开(公告)号：US07437539B2
公开(公告)日：2008-10-14
申请号：US11279777
申请日：2006-04-14
申请人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
发明人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30181 , G06F9/30189 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3861
摘要： An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译：提供了一种用于将处理器置于逐渐减速操作模式的问题单元。逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。处理器逐渐减速使处理器能够突破活动锁定状态。此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

9. 发明授权

US07434033B2 Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline 有权
标题翻译：响应于处理器流水线内检测到的活动锁定状态，将处理器置于逐渐缓慢的操作模式中
公开(公告)号：US07434033B2
公开(公告)日：2008-10-07
申请号：US11279775
申请日：2006-04-14
申请人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
发明人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/524
摘要： Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译：提供了将处理器置于逐渐减速操作模式的机制。逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。处理器逐渐减速使处理器能够突破活动锁定状态。此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

10. 发明申请

US20100262813A1 Detecting and Handling Short Forward Branch Conversion Candidates 审中-公开
标题翻译：检测和处理短期分支转换候选人
公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译：在处理器中提供用于检测和处理短前进分支转换候选的机制。机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。

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