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91. 发明授权

US07582934B2 Isolation spacer for thin SOI devices 有权
标题翻译：用于薄SOI器件的隔离间隔
公开(公告)号：US07582934B2
公开(公告)日：2009-09-01
申请号：US12040877
申请日：2008-03-01
申请人： Chih-Hsin Ko , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
发明人： Chih-Hsin Ko , Wen-Chin Lee , Yee-Chia Yeo , Chung-Hu Ke
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/78618 , Y10S257/90
摘要： A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.
摘要翻译：半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

92. 发明授权

US07511348B2 MOS transistors with selectively strained channels 有权
标题翻译：具有选择性应变通道的MOS晶体管
公开(公告)号：US07511348B2
公开(公告)日：2009-03-31
申请号：US11717450
申请日：2007-03-13
申请人： Chih-Hsin Ko , Wen-Chin Lee , Chung-Hu Ke , Hung-Wei Chen
发明人： Chih-Hsin Ko , Wen-Chin Lee , Chung-Hu Ke , Hung-Wei Chen
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L29/4933 , H01L29/517 , H01L29/665 , H01L29/7843 , H01L29/7845
摘要： The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.
摘要翻译：第一和第二CMOS晶体管的通道可以选择性地受到压力。第一晶体管的栅极结构包括在第一晶体管的沟道中产生应力的应力源。第二晶体管的栅极结构设置成与在第二晶体管的沟道中产生应力的材料层接触。

93. 发明授权

US07466008B2 BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture 有权
标题翻译：通过机械单轴应变的BiCMOS性能提高和制造方法
公开(公告)号：US07466008B2
公开(公告)日：2008-12-16
申请号：US11717484
申请日：2007-03-13
申请人： Chih-Hsin Ko , Tzu-Juei Wang , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
发明人： Chih-Hsin Ko , Tzu-Juei Wang , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
IPC分类号： H01L27/06 , H01L27/07
CPC分类号： H01L21/8249 , H01L21/823807 , H01L27/0623 , H01L29/7843
摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.
摘要翻译：提供了通过机械单轴应变增强性能的BiCMOS器件。本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

94. 发明申请

US20080191285A1 CMOS devices with schottky source and drain regions 审中-公开
标题翻译：具有肖特基源极和漏极区域的CMOS器件
公开(公告)号：US20080191285A1
公开(公告)日：2008-08-14
申请号：US11704402
申请日：2007-02-09
申请人： Chih-Hsin Ko , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
发明人： Chih-Hsin Ko , Hung-Wei Chen , Chung-Hu Ke , Wen-Chin Lee
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823814 , H01L29/1054 , H01L29/165 , H01L29/47 , H01L29/665 , H01L29/6653 , H01L29/66568 , H01L29/6659 , H01L29/66643 , H01L29/7843
摘要： A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device are reduced by forming the PMOS device over a semiconductor layer having a low valence band.
摘要翻译：半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

95. 发明申请

US20070267694A1 Transistors with stressed channels and methods of manufacture 有权
标题翻译：具有应力通道的晶体管和制造方法
公开(公告)号：US20070267694A1
公开(公告)日：2007-11-22
申请号：US11438711
申请日：2006-05-22
申请人： Chih-Hsin Ko , Chung-Hu Ke , Hung-Wei Chen , Wen-Chin Lee
发明人： Chih-Hsin Ko , Chung-Hu Ke , Hung-Wei Chen , Wen-Chin Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7843
摘要： A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.
摘要翻译：提供了在通道区域中具有优化的应力的MOS器件及其形成方法。 MOS器件包括在衬底上的栅极，栅极侧壁上的栅极间隔物，其中在栅极间隔物下方存在非硅化物区域，在衬底中包含凹陷的源极/漏极区域和源极上的硅化物区域 /漏区。在硅化物区域的较高部分和硅化物区域的下部之间形成台阶高度。凹槽与非硅化物区域的相应边缘间隔一定距离。台阶高度和间距优选具有小于或等于约3的比率。非硅化物区域的宽度和台阶高度优选具有小于或等于约3的比率。MOS器件优选为 NMOS器件。

96. 发明授权

US07235838B2 Semiconductor device substrate with embedded capacitor 有权
标题翻译：具有嵌入式电容器的半导体器件衬底
公开(公告)号：US07235838B2
公开(公告)日：2007-06-26
申请号：US10881372
申请日：2004-06-30
申请人： Chun-Chieh Lin , Wen-Chin Lee
发明人： Chun-Chieh Lin , Wen-Chin Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/84 , H01L27/10832 , H01L27/10835 , H01L27/10858 , H01L27/10861 , H01L27/1203 , H01L28/55 , H01L28/82
摘要： A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.
摘要翻译：一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

97. 发明授权

US07208942B2 Magnetism metric controller 失效
标题翻译：磁力公制控制器
公开(公告)号：US07208942B2
公开(公告)日：2007-04-24
申请号：US10991370
申请日：2004-11-19
申请人： Wen-Chin Lee , Shang-Hao Chen
发明人： Wen-Chin Lee , Shang-Hao Chen
IPC分类号： G01B7/30 , G09G5/08
CPC分类号： G06F3/0362
摘要： A precise, consistent, reliable, and high resolution magnetism metric controller applied in electronic and information devices is comprised of a scrolling wheel mechanism to drive by rotation a permanent magnet to retrieve signals of changed magnetic field due to displacement of magnetic poles of the permanent magnet.
摘要翻译：应用于电子信息设备的精确，一致，可靠，高分辨率的磁力度量控制器包括一个滚动轮机构，通过旋转永久磁铁来驱动，以便通过永久磁铁的磁极位移来检索变化的磁场的信号。

98. 发明授权

US07175709B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07175709B2
公开(公告)日：2007-02-13
申请号：US10847099
申请日：2004-05-17
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： C30B25/04
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

99. 发明申请

US20070018259A1 Dual gate electrode metal oxide semciconductor transistors 审中-公开
标题翻译：双栅电极金属氧化物半导体晶体管
公开(公告)号：US20070018259A1
公开(公告)日：2007-01-25
申请号：US11187271
申请日：2005-07-21
申请人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee
发明人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L27/0922
摘要： A semiconductor product includes a pair of field effect transistor device structures formed one each within a pair of doped well regions within a semiconductor substrate. The pair of field effect transistor device structures is formed with a pair of metal gate electrodes formed employing different laminated metal constructions. By correlating a work function within a metal layer within a gate electrode with a work function of a semiconductor substrate region over which it is formed, the field effect transistor devices are formed with enhanced performance.
摘要翻译：半导体产品包括在半导体衬底内的一对掺杂阱区域内形成的一对场效应晶体管器件结构。一对场效应晶体管器件结构由一对使用不同层压金属结构形成的金属栅电极形成。通过将栅电极内的金属层中的功函数与形成在其上的半导体衬底区域的功函数相关联，形成具有增强性能的场效应晶体管器件。

100. 发明申请

US20060248239A1 Data Processing System Capable of Running Two Modes Independently and Exclusively 审中-公开
标题翻译：数据处理系统可独立运行两种模式
公开(公告)号：US20060248239A1
公开(公告)日：2006-11-02
申请号：US11161785
申请日：2005-08-16
申请人： Wen-Chin Lee , Chih-Sheng Huang
发明人： Wen-Chin Lee , Chih-Sheng Huang
IPC分类号： G06F3/00
CPC分类号： G01C21/30
摘要： A data processing system includes a storage device which stores data, a processor which processes application programs and generates decision signals, a bus switch which is coupled with the storage device and the processor, and a processing chip which is coupled with the bus switch, the storage device, and the processor. The data processing system takes advantage of functions of playing media and processing application programs, wherein the functions are designed together with the processing chip. It is more powerful for combining both the functions to increase efficiency of the processor than general data processing system.
摘要翻译：数据处理系统包括存储数据的存储装置，处理应用程序并产生决定信号的处理器，与存储装置和处理器耦合的总线开关，以及与总线开关耦合的处理芯片，存储设备和处理器。数据处理系统利用播放媒体和处理应用程序的功能，其中与处理芯片一起设计功能。结合两种功能来提高处理器的效率比一般数据处理系统更强大。

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