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    • 10. 发明申请
    • Transistors with stressed channels and methods of manufacture
    • 具有应力通道的晶体管和制造方法
    • US20070267694A1
    • 2007-11-22
    • US11438711
    • 2006-05-22
    • Chih-Hsin KoChung-Hu KeHung-Wei ChenWen-Chin Lee
    • Chih-Hsin KoChung-Hu KeHung-Wei ChenWen-Chin Lee
    • H01L29/76
    • H01L29/6656H01L29/66636H01L29/7834H01L29/7843
    • A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.
    • 提供了在通道区​​域中具有优化的应力的MOS器件及其形成方法。 MOS器件包括在衬底上的栅极,栅极侧壁上的栅极间隔物,其中在栅极间隔物下方存在非硅化物区域,在衬底中包含凹陷的源极/漏极区域和源极上的硅化物区域 /漏区。 在硅化物区域的较高部分和硅化物区域的下部之间形成台阶高度。 凹槽与非硅化物区域的相应边缘间隔一定距离。 台阶高度和间距优选具有小于或等于约3的比率。非硅化物区域的宽度和台阶高度优选具有小于或等于约3的比率。MOS器件优选为 NMOS器件。