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91. 发明授权

US06987050B2 Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions 失效
标题翻译：自对准硅化物（自对准硅化物）工艺，用于低电阻接触薄膜绝缘体上硅和体MOSFET以及浅结
公开(公告)号：US06987050B2
公开(公告)日：2006-01-17
申请号：US09902483
申请日：2001-07-11
申请人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
发明人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
IPC分类号： H01L21/331 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/66772 , H01L21/28518 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/78
摘要： A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.
摘要翻译：一种用于制造半导体器件用硅化物的方法（及其结构）包括在硅衬底上沉积金属或其合金，使金属或合金反应形成第一硅化物相，蚀刻任何未反应的金属，沉积硅在第一硅化物相上，使硅帽层反应形成第二硅化物相，并且蚀刻任何未反应的硅。衬底可以是绝缘体上硅（SOI）衬底或体硅衬底。

92. 发明授权

US06905560B2 Retarding agglomeration of Ni monosilicide using Ni alloys 有权
公开(公告)号：US06905560B2
公开(公告)日：2005-06-14
申请号：US10334464
申请日：2002-12-31
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , James M. E. Harper , Christian Lavoie
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , James M. E. Harper , Christian Lavoie
IPC分类号： C04B35/58 , C22F1/00 , C23C10/00 , H01L21/283 , H01L21/285 , H01L21/3205 , H01L21/44 , H01L21/60 , H01L21/768
CPC分类号： C04B35/58 , C04B35/58085 , C04B2235/40 , C04B2235/404 , C04B2235/405 , C04B2235/408 , C23C26/00 , C23C30/00 , H01L21/28518 , H01L21/76889
摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

93. 发明授权

US06809030B2 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06809030B2
公开(公告)日：2004-10-26
申请号：US10185547
申请日：2002-06-28
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

94. 发明授权

US06753606B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US06753606B2
公开(公告)日：2004-06-22
申请号：US09994954
申请日：2001-11-27
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

95. 发明授权

US06555880B2 Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby 有权
标题翻译：自对准硅化物工艺利用离子植入物降低硅消耗，并控制硅化物形成温度和由此形成的结构
公开(公告)号：US06555880B2
公开(公告)日：2003-04-29
申请号：US09875187
申请日：2001-06-07
申请人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
发明人： Cyril Cabral, Jr. , Kevin Kok Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Ronnen Andrew Roy , Paul Michael Solomon
IPC分类号： H01L31119
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L29/41783
摘要： A semiconductor structure includes raised source and drain regions, where the raised source and drain regions are facet free and unconstrained to have a shape conforming to a same crystallographic axes with respect to each other.
摘要翻译：半导体结构包括凸起的源极和漏极区域，其中升高的源极和漏极区域是小面自由的并且不受限制地具有与彼此相同的结晶轴的形状。

96. 发明授权

US06448131B1 Method for increasing the capacitance of a trench capacitor 失效
标题翻译：增加沟槽电容器电容的方法
公开(公告)号：US06448131B1
公开(公告)日：2002-09-10
申请号：US09929182
申请日：2001-08-14
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy M. Cohen , Ramachandra Divakaruni , Christian Lavoie , Fenton R. McFeely
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , H01L29/66181 , Y10S438/964
摘要： A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.
摘要翻译：提供了一种用于增加沟槽电容器表面积的方法。利用金属硅化物粗糙化沟槽壁的方法由于硅化物被去除之后的沟槽表面积的增加而增加了电容。可以通过改变一个或多个以下参数来控制沟槽壁的粗糙化：金属的密度，金属膜厚度，硅化物相以及金属的选择。一旦金属沉积在沟槽中，该方法是自限制的。通过随后的硅沉积或通过硅化物从盖层扩散硅可以获得将沟槽缩小至原始宽度。

97. 发明授权

US09105571B2 Interface engineering to optimize metal-III-V contacts 有权
标题翻译：界面工程优化金属III-V触点
公开(公告)号：US09105571B2
公开(公告)日：2015-08-11
申请号：US13368750
申请日：2012-02-08
申请人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
发明人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
IPC分类号： H01L21/24 , H01L21/225 , H01L21/285 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/20
CPC分类号： H01L21/2258 , H01L21/28575 , H01L29/20 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L2924/0002 , H01L2924/00
摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
摘要翻译：提供了在III-V FET器件中制造自对准触点的技术。一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。在III-V材料的表面上沉积至少一种金属。所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。蚀刻用于去除至少一种金属的任何未反应部分。将至少一种杂质注入到金属III-V合金层中。注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。

98. 发明授权

US09059096B2 Method to form silicide contact in trenches 有权
标题翻译：在沟槽中形成硅化物接触的方法
公开(公告)号：US09059096B2
公开(公告)日：2015-06-16
申请号：US13356090
申请日：2012-01-23
申请人： Michael A. Guillorn , Christian Lavoie , Ghavam G. Shahidi , Bin Yang , Zhen Zhang
发明人： Michael A. Guillorn , Christian Lavoie , Ghavam G. Shahidi , Bin Yang , Zhen Zhang
IPC分类号： H01L23/62 , H01L21/285 , H01L21/8238 , H01L29/417 , H01L29/66 , H01L29/45 , H01L29/786 , H01L23/485 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/76846 , H01L21/76855 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/41725 , H01L29/41733 , H01L29/41775 , H01L29/458 , H01L29/6659 , H01L29/66772 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.
摘要翻译：一种形成硅化物触点的方法包括在栅极间隔物，栅极叠层和第一半导体层上形成电介质层。第一半导体层包括源/漏区。在电介质层中形成接触沟槽，以暴露源/漏区域的至少一部分。在接触沟槽内形成第二半导体层。在第二半导体层上形成金属层。进行退火以在第二半导体层和金属层之间形成硅化物区域。在金属层或硅化物区域上形成导电接触层。

99. 发明授权

US08936978B2 Multigate structure formed with electroless metal deposition 有权
公开(公告)号：US08936978B2
公开(公告)日：2015-01-20
申请号：US12955388
申请日：2010-11-29
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L29/06 , H01L29/417
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

100. 发明授权

US08841652B2 Self aligned carbide source/drain FET 有权
标题翻译：自对准碳化物源极/漏极FET
公开(公告)号：US08841652B2
公开(公告)日：2014-09-23
申请号：US12627120
申请日：2009-11-30
申请人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, Jr. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L29/08 , H01L29/16 , H01L29/775 , B82Y10/00 , H01L51/10 , H01L51/00 , H01L51/05
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译：场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。

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