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1. 发明授权

US07687340B2 Protect diodes for hybrid-orientation substrate structures 失效
标题翻译：用于混合取向衬底结构的保护二极管
公开(公告)号：US07687340B2
公开(公告)日：2010-03-30
申请号：US11849489
申请日：2007-09-04
申请人： James William Adkisson , Jeffrey Peter Gambino , Alain Loiseau , Kirk David Peterson
发明人： James William Adkisson , Jeffrey Peter Gambino , Alain Loiseau , Kirk David Peterson
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.
摘要翻译：半导体结构制造方法。首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向。接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

2. 发明申请

US20090027946A1 METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO) 有权
标题翻译：实现增强SRAM读取性能分析振荡器（PSRO）的方法和设备
公开(公告)号：US20090027946A1
公开(公告)日：2009-01-29
申请号：US11782808
申请日：2007-07-25
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C11/41 , G11C11/419 , G11C2029/0403
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

3. 发明授权

US07411258B2 Cobalt disilicide structure 失效
标题翻译：二硅化钴结构
公开(公告)号：US07411258B2
公开(公告)日：2008-08-12
申请号：US09939895
申请日：2001-08-27
申请人： David Paul Agnello , Mary Conroy Bushey , Donna K. Johnson , Jerome Brett Lasky , Peter James Lindgren , Kirk David Peterson
发明人： David Paul Agnello , Mary Conroy Bushey , Donna K. Johnson , Jerome Brett Lasky , Peter James Lindgren , Kirk David Peterson
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31111 , H01L21/32134
摘要： A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.
摘要翻译：涉及在绝缘栅场效应晶体管（FET）中除去作为形成二硅化钴的工艺的副产物的钛的氧化物的结构。该结构可以包含基本上不含一钴硅酸钴的二硅化钴层，在二硅化钴层上基本上没有钛氧化物的桁条。该结构可以可选地包括一层二硅化钴，一块钛的氧化物和在该温度和一段时间内与该贴片接触的试剂。该层基本上不含一次硅化钴。贴片在二硅化钴层上。试剂适于在一段时间内除去贴剂。试剂不与二硅化钴层发生化学反应，试剂包括水，氢氧化铵和过氧化氢。

4. 发明授权

US06440851B1 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06440851B1
公开(公告)日：2002-08-27
申请号：US09416083
申请日：1999-10-12
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

5. 发明授权

US07696586B2 Cobal disilicide structure 失效
标题翻译：钴二硅化物结构
公开(公告)号：US07696586B2
公开(公告)日：2010-04-13
申请号：US12175549
申请日：2008-07-18
申请人： David Paul Agnello , Mary Conroy Bushey , Donna K. Johnson , Jerome Brett Lasky , Peter James Lindgren , Kirk David Peterson
发明人： David Paul Agnello , Mary Conroy Bushey , Donna K. Johnson , Jerome Brett Lasky , Peter James Lindgren , Kirk David Peterson
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31111 , H01L21/32134
摘要： A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.
摘要翻译：一个结构。该结构可以包括基本上不含一钴硅酸钴的二硅化钴层，并且在二硅化钴层上基本上没有钛氧化物的桁条。该结构可以包括：衬底，其包括：绝缘栅场效应晶体管（FET），其包括源极，漏极和栅极; 在源极上的第二层二硅化钴，所述第一层基本上不含有一氧化硅钴，并且所述第一层在其上基本上不具有钛氧化物的桁条; 漏极上的第二层二硅化锡，所述第二层基本上不具有在其上的钛氧化物基本上没有棱的钴单硅化物; 和在栅极上的第二层二硅化锡，所述第三层基本上不含有一氧化硅钴，并且在其上基本上没有钛氧化物的桁条。

6. 发明授权

US07609542B2 Implementing enhanced SRAM read performance sort ring oscillator (PSRO) 有权
标题翻译：实现增强型SRAM读取性能排序环形振荡器（PSRO）
公开(公告)号：US07609542B2
公开(公告)日：2009-10-27
申请号：US11873534
申请日：2007-10-17
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/40
CPC分类号： G11C11/413
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：一种包括静态随机存取存储器（SRAM）单元的方法和装置实现增强的SRAM读取性能排序环形振荡器（PSRO），以及设置有被摄体电路所在的设计结构。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

7. 发明申请

US20070300082A1 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US20070300082A1
公开(公告)日：2007-12-27
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

8. 发明授权

US06809030B2 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06809030B2
公开(公告)日：2004-10-26
申请号：US10185547
申请日：2002-06-28
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

9. 发明申请

US20080261121A1 PHOTOLITHOGRAPHY MASK WITH PROTECTIVE SILICIDE CAPPING LAYER 审中-公开
标题翻译：具有保护性硅胶覆盖层的光刻胶面板
公开(公告)号：US20080261121A1
公开(公告)日：2008-10-23
申请号：US11738004
申请日：2007-04-20
申请人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
发明人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30 , G03F1/48 , G03F1/54
摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.
摘要翻译：光掩模和制造光掩模的方法。所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。保形层通过氧化形成。

10. 发明申请

US20080261120A1 PHOTOLITHOGRAPHY MASK WITH INTEGRALLY FORMED PROTECTIVE CAPPING LAYER 审中-公开
标题翻译：具有整体形成的保护层的光刻胶面板
公开(公告)号：US20080261120A1
公开(公告)日：2008-10-23
申请号：US11737956
申请日：2007-04-20
申请人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
发明人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30 , G03F1/48 , G03F1/54
摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.
摘要翻译：光掩模和制造光掩模的方法。所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。保形层通过氧化形成。

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