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91. 发明授权

US07355441B1 Programmable logic devices with distributed memory and non-volatile memory 有权
标题翻译：具有分布式存储器和非易失性存储器的可编程逻辑器件
公开(公告)号：US07355441B1
公开(公告)日：2008-04-08
申请号：US11360337
申请日：2006-02-22
申请人： Om P. Agrawal , Brad Sharpe-Geisler , Jye-Yuh Lee , Bai Nguyen
发明人： Om P. Agrawal , Brad Sharpe-Geisler , Jye-Yuh Lee , Bai Nguyen
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728
摘要： Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure, with at least one block of non-volatile memory to store configuration data that can be transferred to the configuration memory cells.
摘要翻译：根据本发明的一个或多个实施例公开了系统和方法，以向可编程逻辑器件提供非易失性存储器和可变量的分布式存储器（例如，以成本有效的方式）。例如，根据本发明的实施例，可编程逻辑器件包括提供用于可编程逻辑器件的输入/输出接口的多个输入/输出块以及提供可编程逻辑功能的第一和第二多个逻辑块，只有第二多个逻辑块进一步适于提供随机存取存储器功能。路由结构可编程地将输入/输出块与第一和第二多个逻辑块相互连接。配置存储器单元存储配置数据以配置输入/输出块，第一和第二多个逻辑块以及路由结构，具有至少一个非易失性存储器块以存储可以传送到配置存储器的配置数据细胞。

92. 发明授权

US07208975B1 SERDES with programmable I/O architecture 有权
标题翻译： SERDES具有可编程I / O架构
公开(公告)号：US07208975B1
公开(公告)日：2007-04-24
申请号：US11040772
申请日：2005-01-20
申请人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
发明人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.
摘要翻译：在一个实施例中，可编程互连包括专用于传送高速数据的SERDES电路和专用于传送低速数据的输入/输出（I / O）电路。布线结构可配置为将SERDES电路耦合到另一个SERDES电路，到I / O电路的SERDES电路，到SERDES电路的I / O电路以及通过路由路径到另一个I / O电路的I / O电路具有确定性的路由延迟。在另一个实施例中，路由结构包括用于向SERDES电路传送高速数据和从SERDES电路传送高速数据的高速路由结构以及用于向I / O电路传送低速数据的低速路由结构。

93. 发明授权

US07088134B1 Programmable logic device with flexible memory allocation and routing 有权
标题翻译：可编程逻辑器件，具有灵活的存储器分配和路由
公开(公告)号：US07088134B1
公开(公告)日：2006-08-08
申请号：US10704025
申请日：2003-11-06
申请人： Om P. Agrawal , Jason Cheng , Paul R. Bonwick , Bradley Felton , Andrew Armitage
发明人： Om P. Agrawal , Jason Cheng , Paul R. Bonwick , Bradley Felton , Andrew Armitage
IPC分类号： H01L25/01
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/17736
摘要： A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.
摘要翻译：可编程逻辑器件包括组织成簇的多个逻辑块。每个逻辑块可以被配置为逻辑模式和存储器模式。逻辑块被布置成至少一个簇，每个簇具有被配置为向其簇内的逻辑块提供数据字的数据总线。

94. 发明授权

US07081771B2 Upgradeable and reconfigurable programmable logic device 有权
公开(公告)号：US07081771B2
公开(公告)日：2006-07-25
申请号：US10783886
申请日：2004-02-20
申请人： Om P. Agrawal , Howard Tang , Jack Wong
发明人： Om P. Agrawal , Howard Tang , Jack Wong
IPC分类号： H03K19/177
CPC分类号： H03K19/17772 , H03K19/17732 , H03K19/1776 , H03K19/17768
摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

95. 发明授权

US06703860B1 I/O block for a programmable interconnect circuit 有权
标题翻译：用于可编程互连电路的I / O块
公开(公告)号：US06703860B1
公开(公告)日：2004-03-09
申请号：US10021844
申请日：2001-12-14
申请人： Om P. Agrawal , Jinghui Zhu
发明人： Om P. Agrawal , Jinghui Zhu
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： A programmable interconnect circuit comprising a plurality of I/O cells arranged into I/O blocks includes a routing structure for each I/O block, wherein each routing structure may programmably route signals between the plurality of I/O cells and the I/O cells within its I/O block. Each I/O cell includes a multiplexer and an I/O circuit associated with a pin of the programmable interconnect circuit. Associated with each I/O block is a control array receiving control signals from its routing structure. An AND array in the control array produces a set of product term control signals for its I/O block from the received control signals.
摘要翻译：包括布置在I / O块中的多个I / O单元的可编程互连电路包括用于每个I / O块的路由结构，其中每个路由结构可编程地在多个I / O单元与I / O单元之间路由信号其I / O块内的单元。每个I / O单元包括多路复用器和与可编程互连电路的引脚相关联的I / O电路。与每个I / O块相关联的是从其路由结构接收控制信号的控制阵列。控制阵列中的AND阵列从接收的控制信号产生一组其I / O块的产品项控制信号。

96. 发明授权

US06653860B2 Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures 有权
标题翻译：具有可扩展产品术语共享能力的增强宏单元模块，用于高密度CPLD架构
公开(公告)号：US06653860B2
公开(公告)日：2003-11-25
申请号：US09927793
申请日：2001-08-10
申请人： Om P. Agrawal , Xiaojie (Warren) He , Claudia A. Stanley , Larry R. Metzger , Chong M. Lee
发明人： Om P. Agrawal , Xiaojie (Warren) He , Claudia A. Stanley , Larry R. Metzger , Chong M. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/1737 , H03K19/177
摘要： An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g., ≦5 PT's) to having slower generation of sums of a much larger number of PT's (e.g., ≦160 PT's).
摘要翻译：改进的高密度CPLD包括多个宏单元部分。每个宏小区部分可以接收相对大量的独立输入项，并且可以生成至少多达5个不同产品项信号（PT）作为基本簇。宏单元本地5 PT的部分或全部可用于在本地一级ORring操作中生成本地产品（SoP）产品（SoP）信号。另外，在相邻宏小区部分中生成的SoP可以被选择性地和递增级联（交叉），以用于对本地SoP信号的补充求和。可以在用于第二级求和的和共享阵列中进一步选择相邻部分的SoP信号。第一级级联（交错法）和二级总和共享的组合提供了广泛的可编程选择的粒度，包括相对较快地生成仅几个PT的总和（例如，<= 5PT）要产生更大数量的PT（例如，<= 160 PT'S）的总和的较慢的产生。

97. 发明授权

US06650142B1 Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use 有权
标题翻译：增强的CPLD宏单元模块具有基于转向的资源分配和使用方法的可选旁路
公开(公告)号：US06650142B1
公开(公告)日：2003-11-18
申请号：US10219046
申请日：2002-08-13
申请人： Om P. Agrawal , Fabiano Fontana , Gilles M. Bosco
发明人： Om P. Agrawal , Fabiano Fontana , Gilles M. Bosco
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736
摘要： Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≧80 PT's) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps-of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.
摘要翻译：提供了结构和技术，用于允许在复杂可编程逻辑器件（CPLD）中发生以下动作中的一个或多个：（1）选择使用快速的分配器旁路路径（例如，快速5-PT路径）结合块内简单或超分配; （2）为不需要引脚一致性的信号选择使用OSM旁路; （3）自动重新路由输出使能信号，对应于输出信号，这些信号被重新路由以达到引脚一致性的目的; （4）全球可用的输出使能信号的全球分布; （5）选择性使用两级转向来开发复杂的总和集合术语，其中快速路径或简单分配是不够的; 和（6）在每个逻辑块具有约24个或更少的宏单元单元的设计中使用具有阶段2环绕的单向超分配。提供了用于集中复杂功能信号（例如，> = 80PT）的奇异逻辑块的开发的技术，使得这种复杂功能信号的发展不消耗块间互连资源。一种CPLD配置方法包括机器实现的步骤 - 首先识别通过在一个逻辑块中的组合简单或超分配开发可实现的中间复杂度功能，以及在相同或第二逻辑块中的快速路径完成; 以及配置CPLD以通过在一个逻辑块中的简单或超分配开发实现在第一识别步骤中识别的一个或多个功能，并且在相同或第二逻辑块中实现快速路径完成。

98. 发明授权

US6028446A Flexible synchronous and asynchronous circuits for a very high density programmable logic device 失效
标题翻译：灵活的同步和异步电路，用于非常高密度的可编程逻辑器件
公开(公告)号：US6028446A
公开(公告)日：2000-02-22
申请号：US118200
申请日：1998-07-17
申请人： Om P. Agrawal , Kerry A. Ilgenstein
发明人： Om P. Agrawal , Kerry A. Ilgenstein
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1774
摘要： A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the appropriate product term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.
摘要翻译：可编程逻辑器件（PLD）单元用于构建高密度高性能可编程逻辑器件（PLD）。 PLD单元包括两个可编程逻辑块单元。 PLD单元还包括I / O单元和输入宏单元。此外，PLD单元包括可编程输出开关矩阵组的子组和可编程输入开关矩阵组的子组。每个可编程逻辑块单元包括多个乘积项。集群中至少有一个产品术语可编程地可用于集群。当产品术语与集群断开连接时，产品术语用于控制逻辑宏单元输出信号或异步功能的极性。因此，可编程可连接产品术语可用于同步或异步操作。如果可编程可连接和可断开的产品术语连接到产品术语集群，则可编程逻辑块单元用于同步操作。然而，由于每个产品项集合与逻辑宏单元相关联，所以逻辑宏单元可以通过简单地从产品项集群中断开适当的产品项并使用所需的异步功能的乘积项来单独配置用于异步操作。因此，使用可编程逻辑块单元构建的单个PLD同时支持同步和异步操作。

99. 发明授权

US5587921A Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer 失效
标题翻译：每个可配置逻辑块的阵列包括具有耦合到第一多路复用器并且具有耦合到第二多路复用器的输出的输入的查找表
公开(公告)号：US5587921A
公开(公告)日：1996-12-24
申请号：US560933
申请日：1995-11-20
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a lookup table having inputs and outputs, a first multiplexer means for applying a selected subset of CLB input signals to the lookup table inputs, and a second multiplexer means for routing lookup table output signals to selectable destinations. The first multiplexer means can programmably route input signals to the lookup table inputs from a variety of sources including first through fourth direct-connect receiving terminals distributed symmetrically about the CLB, first through fourth longline receiving terminals distributed symmetrically about the CLB, first through fourth general-interconnect receiving terminals distributed symmetrically about the CLB, and first through fourth feedback means distributed symmetrically within the CLB. The second multiplexer means can programmably route output signals from the lookup table to first through fourth output macrocells distributed symmetrically about the CLB. The first through fourth output macrocells can respectively couple the routed signals to first through fourth direct-connect outputting terminals distributed symmetrically about the CLB, first through fourth tristate outputting terminals distributed symmetrically about the CLB, and the first through fourth feedback means.
摘要翻译：可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。每个CLB包括具有输入和输出的查找表，用于将选定的CLB输入信号的子集应用于查找表输入的第一多路复用器装置和用于将查找表输出信号路由到可选目的地的第二多路复用器装置。第一多路复用器装置可编程地将输入信号路由到各种源的查找表输入，包括关于CLB对称分布的第一至第四直接接收终端，关于CLB对称分布的第一至第四延长线接收终端，第一至第四通用 - 关于CLB对称分布的接收端子以及在CLB内对称分布的第一至第四反馈装置。第二多路复用器装置可编程地将来自查找表的输出信号路由到关于CLB对称分布的第一到第四输出宏小区。第一到第四输出宏单元可以分别将路由信号耦合到关于CLB对称地分布的第一到第四直接连接输出端子，关于CLB对称地分布的第一到第四三态输出端子以及第一到第四反馈装置。

100. 发明授权

US5426335A Pinout architecture for a family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix 失效
标题翻译：用于通过高速集中式交换矩阵互连的多分段可编程逻辑块系列的引脚分配架构
公开(公告)号：US5426335A
公开(公告)日：1995-06-20
申请号：US85601
申请日：1993-06-30
申请人： Om P. Agrawal , Kerry A. Ingenstein
发明人： Om P. Agrawal , Kerry A. Ingenstein
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17708 , H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744
摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.
摘要翻译：至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

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