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1. 发明授权

US07459935B1 Programmable logic devices with distributed memory 有权
标题翻译：具有分布式存储器的可编程逻辑器件
公开(公告)号：US07459935B1
公开(公告)日：2008-12-02
申请号：US12060776
申请日：2008-04-01
申请人： Om P. Agrawal , Brad Sharpe-Geisler , Jye-Yuh Lee , Bai Nguyen
发明人： Om P. Agrawal , Brad Sharpe-Geisler , Jye-Yuh Lee , Bai Nguyen
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728
摘要： A programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide distributed random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure. In one embodiment, there are at least twice as many logic blocks in the first plurality of logic blocks than in the second plurality of logic blocks. In another embodiment, the first and second plurality of logic blocks are arranged in one or more rows, and the programmable logic device includes one or more rows of embedded block RAM.
摘要翻译：可编程逻辑器件包括提供用于可编程逻辑器件的输入/输出接口和提供可编程逻辑功能的第一和第二多个逻辑块的多个输入/输出块，只有第二多个逻辑块进一步适于提供分布式随机存取功能。路由结构可编程地将输入/输出块与第一和第二多个逻辑块相互连接。配置存储器单元存储配置数据以配置输入/输出块，第一和第二多个逻辑块以及路由结构。在一个实施例中，在第一多个逻辑块中比在第二多个逻辑块中存在至少两倍的逻辑块。在另一个实施例中，第一和第二多个逻辑块被布置成一行或多行，并且可编程逻辑器件包括一行或多行嵌入块RAM。

2. 发明授权

US07355441B1 Programmable logic devices with distributed memory and non-volatile memory 有权
标题翻译：具有分布式存储器和非易失性存储器的可编程逻辑器件
公开(公告)号：US07355441B1
公开(公告)日：2008-04-08
申请号：US11360337
申请日：2006-02-22
申请人： Om P. Agrawal , Brad Sharpe-Geisler , Jye-Yuh Lee , Bai Nguyen
发明人： Om P. Agrawal , Brad Sharpe-Geisler , Jye-Yuh Lee , Bai Nguyen
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728
摘要： Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure, with at least one block of non-volatile memory to store configuration data that can be transferred to the configuration memory cells.
摘要翻译：根据本发明的一个或多个实施例公开了系统和方法，以向可编程逻辑器件提供非易失性存储器和可变量的分布式存储器（例如，以成本有效的方式）。例如，根据本发明的实施例，可编程逻辑器件包括提供用于可编程逻辑器件的输入/输出接口的多个输入/输出块以及提供可编程逻辑功能的第一和第二多个逻辑块，只有第二多个逻辑块进一步适于提供随机存取存储器功能。路由结构可编程地将输入/输出块与第一和第二多个逻辑块相互连接。配置存储器单元存储配置数据以配置输入/输出块，第一和第二多个逻辑块以及路由结构，具有至少一个非易失性存储器块以存储可以传送到配置存储器的配置数据细胞。

3. 发明授权

US07787326B1 Programmable logic device with a multi-data rate SDRAM interface 有权
标题翻译：具有多数据速率SDRAM接口的可编程逻辑器件
公开(公告)号：US07787326B1
公开(公告)日：2010-08-31
申请号：US12019526
申请日：2008-01-24
申请人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
发明人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
IPC分类号： G11C8/18
CPC分类号： G06F13/4243
摘要： Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.
摘要翻译：在可编程逻辑器件中，诸如DDR SDRAM接口的多数据速率SDRAM接口在一个实施例中包括DQS时钟树，从延迟电路和延迟锁定环（DLL）。从延迟电路适于相对于数据相位移位DQS信号的相位，以向DQS时钟树提供相移DQS信号，并且该DLL适于控制从延迟电路。该DLL包括延迟线，其包括从延迟电路的多个实例和DQS时钟树的多个传真机。

4. 发明授权

US07342838B1 Programmable logic device with a double data rate SDRAM interface 有权
标题翻译：具有双数据速率SDRAM接口的可编程逻辑器件
公开(公告)号：US07342838B1
公开(公告)日：2008-03-11
申请号：US11165853
申请日：2005-06-24
申请人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
发明人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
IPC分类号： G11C7/00
CPC分类号： G06F13/4243
摘要： Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.
摘要翻译：在可编程逻辑器件（PLD）中，提供用于DDR SDRAM的DDR SDRAM接口，DDR SDRAM在DQS信号的上升沿和下降沿向PLD提供数据，该接口包括：适于捕获数据的第一寄存器与DQS信号的下降沿相关联; 第二寄存器，其适于捕获与所述DQS信号的上升沿相关联的数据; 以及时钟沿选择逻辑电路，其耦合到第一和第二寄存器的时钟输入，并且适于在内部PLD时钟的上升沿或下降时钟沿之间进行选择，以对第一和第二寄存器进行时钟，从而将捕获的数据传输到核心逻辑 PLD，根据内部PLD时钟和DQS信号之间的相位关系选择时钟沿。

5. 发明授权

US07098685B1 Scalable serializer-deserializer architecture and programmable interface 有权
标题翻译：可扩展串行器 - 解串器架构和可编程接口
公开(公告)号：US07098685B1
公开(公告)日：2006-08-29
申请号：US10619645
申请日：2003-07-14
申请人： Om P. Agrawal , Bai Nguyen , Kuang Chi , Brad Sharpe-Geisler , Giap Tran
发明人： Om P. Agrawal , Bai Nguyen , Kuang Chi , Brad Sharpe-Geisler , Giap Tran
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/00 , H01L25/00
CPC分类号： H03K19/17744 , H03M9/00
摘要： Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery circuit. The programmable interface further includes programmable input/output buffers and embedded memory to allow the programmable logic device to support a wide range of input/output interface standards.
摘要翻译：公开了提供可编程逻辑器件的可编程输入/输出功能的系统和方法。例如，根据本发明的一个实施例，可编程接口选择性地采用可伸缩串行器 - 解串器和时钟和数据恢复电路。可编程接口还包括可编程输入/输出缓冲器和嵌入式存储器，以允许可编程逻辑器件支持大范围的输入/输出接口标准。

6. 发明授权

US07256613B1 Programmable interconnect architecture for programmable logic devices 有权
标题翻译：可编程逻辑器件的可编程互连架构
公开(公告)号：US07256613B1
公开(公告)日：2007-08-14
申请号：US11165709
申请日：2005-06-24
申请人： Brad Sharpe-Geisler , Om P. Agrawal , Cindy Lee
发明人： Brad Sharpe-Geisler , Om P. Agrawal , Cindy Lee
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： In one embodiment of the invention, a programmable logic device (PLD) includes a plurality of programmable logic blocks arrayed in rows and columns, wherein each programmable logic block is coupled to a corresponding vertical routing resource and a corresponding horizontal routing resource, and wherein each vertical and horizontal routing resource includes a plurality of wires organized into wire groups and each programmable logic block has a set of inputs organized into input groups. The PLD also includes a plurality of connection boxes, each connection box corresponding to a programmable logic block and operable to couple a given wire group in one of the corresponding vertical and horizontal routing resources to a given input group independently of whether a given wire group in the remaining one of the corresponding vertical and horizontal routing resources is coupled through the connection box to the given input group.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件（PLD）包括以行和列排列的多个可编程逻辑块，其中每个可编程逻辑块耦合到对应的垂直路由资源和对应的水平路由资源，并且其中每个垂直和水平路由资源包括组织成有线组的多个线，并且每个可编程逻辑块具有被组织成输入组的一组输入。 PLD还包括多个连接盒，每个连接盒对应于可编程逻辑块，并且可操作以将相应垂直和水平路由资源之一中的给定线组耦合到给定的输入组，而不管给定的线组是否在相应的垂直和水平路由资源中的剩余的一个通过连接盒耦合到给定的输入组。

7. 发明授权

US06204686B1 Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources 有权
标题翻译：用于配置具有可变粒度块和共享逻辑的FPGA的方法，用于将结果输出的对称路由提供给不同方向和可三态互连资源
公开(公告)号：US06204686B1
公开(公告)日：2001-03-20
申请号：US09216662
申请日：1998-12-16
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Herman M. Chang , Bai Nguyen , Giap H. Tran
IPC分类号： G06F738
CPC分类号： H03K19/17756 , H03K19/17736
摘要： A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.
摘要翻译：可变粒度结构（VGA）设备包括共享输出组件（SOC），其可以用于将处理结果信号可编程地路由到FPGA内的不同定向长线中的一个或多个上。多个VGB共享使用每个SOC，以将相应的功能信号输出到延绳。 SOC也可用于可编程地路由选择性地从等效但不同位置的互连通道中的任一个获取的信号（例如，馈通信号）。路由VGB结果信号或馈通信号的这种自由可以允许FPGA配置软件探索更广泛的分区，布局和/或布线选项，以便在各种提供的设计规范的VGA FPGA器件中找到优化的实现。

8. 发明授权

US06163168A Efficient interconnect network for use in FPGA device having variable grain architecture 有权
标题翻译：高效互连网络，用于具有可变粒度架构的FPGA器件
公开(公告)号：US06163168A
公开(公告)日：2000-12-19
申请号：US208203
申请日：1998-12-09
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.
摘要翻译：逻辑阵列器件具有多个互连资源的阵列，包括多个线路和多个开关盒区域，多个可变格栅块（VGB）的阵列散布在多个互连资源的阵列内。多个互连资源的阵列不规则地包括单个长度或更短的线，并且多个互连资源的阵列不规则地包括通过单个长度或更短的距离彼此间隔开的开关盒区域。单个长度对应于覆盖大约一个VGB的连续距离的横越。

9. 发明授权

US06154051A Tileable and compact layout for super variable grain blocks within FPGA device 有权
标题翻译： FPGA器件内的超可变晶粒块的平铺紧凑布局
公开(公告)号：US06154051A
公开(公告)日：2000-11-28
申请号：US187689
申请日：1998-11-05
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
IPC分类号： H01L27/02 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H01L27/0207 , H03K19/1778 , H03K19/17796
摘要： A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.
摘要翻译：为逻辑阵列器件提供了可瓦片结构。可瓦片结构具有逻辑块集合的逻辑对称布置，用于逻辑块集合的公共控制部分，周围互连线以及互连线的交叉处的交换区域。

10. 发明授权

US06181163B2 FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals 有权
标题翻译： FPGA集成电路具有嵌入式SRAM存储块和用于广播地址和控制信号的互连通道
公开(公告)号：US06181163B2
公开(公告)日：2001-01-30
申请号：US09235351
申请日：1999-01-21
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。

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