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91. 发明授权

US5851883A High density integrated circuit process 失效
标题翻译：高密度集成电路工艺
公开(公告)号：US5851883A
公开(公告)日：1998-12-22
申请号：US844975
申请日：1997-04-23
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.
摘要翻译：在包括硅基层的半导体衬底的上表面上形成介电层的半导体工艺。此后，在电介质层的上表面上形成上硅层。然后对电介质层和上硅层进行构图以在基底硅层的上表面上形成第一和第二硅 - 电介质叠层。第一和第二硅 - 电介质堆叠在硅衬底的沟道区域的任一侧上横向移位，并且每个包括近侧壁和远侧壁。近侧侧壁与通道区域的各个边界大致重合。此后，分别在第一和第二硅 - 电介质堆叠的近侧和远侧壁上形成近端和远端间隔结构。然后在硅基层的暴露部分上在基底硅层的沟道区上形成栅极电介质层。然后选择性地去除位于基底硅层的相应源极/漏极区域之上的第一和第二硅 - 电介质叠层的部分。然后沉积硅以填充由所选择的堆叠移除产生的第一和第二空隙。硅沉积还在沟道区域上填充栅极电介质上方的硅栅极区域。此后，将杂质分布引入沉积的硅中。沉积的硅然后被平坦化以物理地隔离第一和第二空隙内的栅极区域内的硅，从而形成包括硅栅极结构和第一和第二源极/漏极结构的晶体管。

92. 发明授权

US5834350A Elevated transistor fabrication technique 失效
公开(公告)号：US5834350A
公开(公告)日：1998-11-10
申请号：US873116
申请日：1997-06-11
申请人： Mark I. Gardner , Daniel Kadosh , Michael Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael Duane
IPC分类号： H01L21/822 , H01L27/06 , H01L21/336
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

93. 发明授权

US5677224A Method of making asymmetrical N-channel and P-channel devices 失效
标题翻译：制造不对称N沟道和P沟道器件的方法
公开(公告)号：US5677224A
公开(公告)日：1997-10-14
申请号：US711381
申请日：1996-09-03
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/70
CPC分类号： H01L21/823814 , H01L27/0922
摘要： An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped source region and lightly doped drain region provide channel junctions. Forming a first asymmetrical IGFET includes forming a gate with first and second opposing sidewalls over a first active region, applying a first ion implantation to implant lightly doped source and drain regions into the first active region, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. A second asymmetrical IGFET is formed in a related manner. Advantageously, one or both IGFETs have low source-drain series resistance and reduce hot carrier effects.
摘要翻译：公开了非对称N沟道IGFET和非对称P沟道IGFET。一个或两个IGFET包括轻掺杂漏极区，重掺杂源极和漏极区以及超重掺杂源极区。优选地，重掺杂源极区域和轻掺杂漏极区域提供沟道结。形成第一不对称IGFET包括在第一有源区上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂源极和漏极区域注入到第一有源区中，施加第二离子注入以将所述轻掺杂源区分别成为重掺杂源区，而不掺杂所述轻掺杂漏区，分别与所述第一和第二侧壁相邻形成第一和第二间隔区，并施加第三离子注入以转换所述重掺杂源区的一部分在第一间隔物之外的第一间隔物外部，而不掺杂第一间隔物下面的重掺杂源区的一部分，并将第二间隔区外部的轻掺杂漏极区的一部分转换成重掺杂漏极区，而不掺杂第二间隔物下面的轻掺杂漏极区的一部分。以相关的方式形成第二不对称IGFET。有利地，一个或两个IGFET具有低的源 - 漏串联电阻并且减少热载流子效应。

94. 发明授权

US5654215A Method for fabrication of a non-symmetrical transistor 失效
标题翻译：制造非对称晶体管的方法
公开(公告)号：US5654215A
公开(公告)日：1997-08-05
申请号：US713388
申请日：1996-09-13
申请人： Mark I. Gardner , Daniel Kadosh , Robert Dawson
发明人： Mark I. Gardner , Daniel Kadosh , Robert Dawson
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823468 , H01L29/7835 , Y10S438/911
摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, a gate insulator and a gate electrode, such as a polysilicon, are formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall. First and second symmetrical spacers are then formed adjacent the first and second sidewalls, respectively. A second dopant is implanted into the semiconductor substrate after forming the symmetrical spacers to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer. After implanting the second dopant, first and second non-symmetrical spacers are formed adjacent the first and second sidewalls, respectively. A heavy dose of a third dopant is then implanted into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region. In another embodiment, a fourth dopant is implanted into the semiconductor substrate before forming the first and second symmetrical spacers further doping the lightly doped drain region.
摘要翻译：在本发明中，描述了用于制造非对称LDD-IGFET的方法。在一个实施例中，栅极绝缘体和诸如多晶硅的栅电极形成在半导体衬底之上，栅电极具有顶表面和相对的第一和第二侧壁。将第一掺杂剂注入到半导体衬底中以提供基本上与第二侧壁对齐的轻掺杂漏极区。然后分别在第一和第二侧壁附近形成第一和第二对称间隔物。在形成对称间隔物之后，将第二掺杂剂注入到半导体衬底中，以提供基本上与第二对称间隔物的外部区域对准的适度轻掺杂的漏区。在注入第二掺杂剂之后，分别在第一和第二侧壁附近形成第一和第二非对称间隔物。然后将大量的第三掺杂剂注入到半导体衬底中以提供重掺杂的源极区域和重掺杂的漏极区域。在另一个实施例中，在形成第一和第二对称间隔物之前将第四掺杂剂注入到半导体衬底中，进一步掺杂轻掺杂漏极区。

95. 发明授权

US06358828B1 Ultra high density series-connected transistors formed on separate elevational levels 失效
标题翻译：超高密度串联晶体管形成在不同的高程
公开(公告)号：US06358828B1
公开(公告)日：2002-03-19
申请号：US09118514
申请日：1998-07-17
申请人： Daniel Kadosh , Mark I. Gardner
发明人： Daniel Kadosh , Mark I. Gardner
IPC分类号： H01L213205
CPC分类号： H01L27/0688
摘要： A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.
摘要翻译：提供三维集成电路和制造工艺，用于在集成电路的各种级别上产生有源和无源器件。本方法特别适用于将一个晶体管的源极互连到另一个晶体管的漏极，以形成通常用于核心逻辑单元的串联连接的晶体管。底层晶体管的结可以连接到上覆晶体管的结，两个晶体管由层间电介质分隔开。下部晶体管结使用插头导体连接到上层晶体管结。插头导体，更确切地说，相互连接的连接部分进一步耦合到横向延伸的互连。互连从插头导体的相互连接点延伸到上覆晶体管的衬底。因此，覆盖晶体管的源极和衬底可以连接到下面的晶体管的漏极，以便不仅实现串联连接，而且连接内部构造的晶体管的源极和衬底以减少体效应。

96. 发明授权

US06300661B1 Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate 失效
标题翻译：用于将功率/接地施加到晶体管的源极和基底阱的相互注入区域
公开(公告)号：US06300661B1
公开(公告)日：2001-10-09
申请号：US09060509
申请日：1998-04-14
申请人： Daniel Kadosh , Mark I. Gardner , Michael P. Duane
发明人： Daniel Kadosh , Mark I. Gardner , Michael P. Duane
IPC分类号： H01L2976
CPC分类号： H01L21/823425 , H01L21/823493 , H01L27/088 , Y10S257/928
摘要： An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region. Also, merging a portion of the well-tie region with a portion of the source region affords increased packing density of an integrated circuit. The higher packing density is achieved without resorting to decreasing the dimensions of the well-tie region, and thus without detrimentally increasing the resistance of the well-tie region.
摘要翻译：提供了一种集成电路制造工艺，用于在阱内形成由位于阱内的晶体管的源极区域和耦合到阱的阱区域共享的阱内的相互注入区域，从而提供到该阱的单个电连接井和源区。触点可以耦合到相互植入区域，并且导体可以连接到触点。在阱是其中形成NMOS晶体管的p型阱的情况下，可以将接地电压施加到导体以偏置源极区域和阱。另一方面，如果阱是其中形成有PMOS晶体管的n型阱，则可以将电源电压VCC施加到导体以偏置源极区域和阱。不需要形成与源极区域和连接区域的接触以及与这些触点的导体的接触，所以需要较少的空间来偏置阱和源极区域。而且，将一部分连接区域与源区域的一部分合并，可以提高集成电路的堆积密度。填充密度更高，而不需要减小连接区域的尺寸，从而不会不利地增加连接区域的阻力。

97. 发明授权

US6096591A Method of making an IGFET and a protected resistor with reduced processing steps 失效
标题翻译：制造IGFET和受保护电阻的方法，减少加工步骤
公开(公告)号：US6096591A
公开(公告)日：2000-08-01
申请号：US911746
申请日：1997-08-15
申请人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8234
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the gate and the diffused resistor, forming a masking layer over the insulating layer that covers the resistor region and includes an opening above the active region, applying an etch using the masking layer as an etch mask so that unetched portions of the insulating layer over the active region form spacers in close proximity to opposing sidewalls of the gate and an unetched portion of the insulating layer over the resistor region forms a resistor-protect insulator, and forming a source and a drain in the active region. In this manner, a single insulating layer provides both sidewall spacers for the gate and a resistor-protect insulator for the diffused resistor.
摘要翻译：制造IGFET和受保护电阻器的方法包括向半导体衬底提供有源区和电阻区，在有源区上形成栅极，在电阻区中形成扩散电阻，在栅极上形成绝缘层，扩散电阻器，在覆盖电阻器区域的绝缘层上形成掩模层，并且在有源区域上方包括开口，使用掩模层施加蚀刻作为蚀刻掩模，使得在有源区域上的绝缘层的未蚀刻部分形成间隔物靠近栅极的相对侧壁并且在电阻器区域上的绝缘层的未蚀刻部分形成电阻器保护绝缘体，并且在有源区域中形成源极和漏极。以这种方式，单个绝缘层提供用于栅极的两个侧壁间隔件和用于扩散电阻器的电阻保护绝缘体。

98. 发明授权

US6080640A Metal attachment method and structure for attaching substrates at low temperatures 失效
标题翻译：用于在低温下安装基板的金属附着方法和结构
公开(公告)号：US6080640A
公开(公告)日：2000-06-27
申请号：US45324
申请日：1998-03-20
申请人： Mark I. Gardner , Fred Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred Hause , Daniel Kadosh
IPC分类号： H01L21/768 , H01L21/98 , H01L23/532 , H01L25/065 , H01L21/30 , H01L21/46
CPC分类号： H01L25/50 , H01L21/76801 , H01L21/76834 , H01L23/5329 , H01L24/80 , H01L25/0657 , H01L2224/05571 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06541 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3011
摘要： A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from is the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.
摘要翻译：高密度集成电路结构及其制造方法包括提供具有根据第一电路实现的半导体器件结构的第一硅衬底结构和设置在其顶表面上的金属层间线以及具有第二电路的第二硅衬底结构实施和设置在其顶表面上的金属层间线。第一衬底结构包括布置在金属层间线之间的平坦化低K电介质和将金属层间线与低K电介质隔开的保护涂层，第一硅衬底结构的金属层间线具有在介电K值在2.0-3.8范围内的低K电介质。第二基板结构还包括布置在金属层间线之间的平坦化的低K电介质和将金属层间线与低K电介质隔开的保护涂层，金属层间线具有小于500°的熔融温度并且介电K值在2.0-3.8范围内的低K电介质。最后，第一衬底结构在第一和第二衬底结构的相应的金属层间线处被低温地结合到第二衬底结构。

99. 发明授权

US6069398A Thin film resistor and fabrication method thereof 失效
标题翻译：薄膜电阻及其制造方法
公开(公告)号：US6069398A
公开(公告)日：2000-05-30
申请号：US905306
申请日：1997-08-01
申请人： Daniel Kadosh , Mark I. Gardner , Frederick N. Hause
发明人： Daniel Kadosh , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/02 , H01L27/06 , H01L29/00
CPC分类号： H01L28/20 , H01L27/0688
摘要： A resistor is formed between devices in an integrated circuit by forming a patterned trench in an intralayer dielectric (ILD) deposited over the devices, filling the trench with polysilicon and planarizing the polysilicon. The resistance of the resistor is defined by determining and selecting the size and form of the trench including the width, length, depth and orientation of the trench. In some embodiments, the resistance of the resistor is also controlled by adding selected amounts and species of dopants to the polysilicon. In some embodiments, the resistance is controlled by directly saliciding the polysilicon in the trench.
摘要翻译：通过在沉积在器件上的层间电介质（ILD）中形成图案化沟槽，用多晶硅填充沟槽并平坦化多晶硅，在集成电路中的器件之间形成电阻器。通过确定和选择包括沟槽的宽度，长度，深度和取向的沟槽的尺寸和形式来限定电阻器的电阻。在一些实施例中，电阻器的电阻也通过将选定量和种类的掺杂剂添加到多晶硅来控制。在一些实施例中，通过在沟槽中直接浇注多晶硅来控制电阻。

100. 发明授权

US6051876A Semiconductor device with a graded passivation layer 失效
标题翻译：具有渐变钝化层的半导体器件
公开(公告)号：US6051876A
公开(公告)日：2000-04-18
申请号：US2651
申请日：1998-01-05
申请人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
发明人： Mark I. Gardner , Sey Ping Sun , Daniel Kadosh
IPC分类号： H01L23/31 , H01L23/48
CPC分类号： H01L23/3171 , H01L2924/0002 , H01L2924/13091
摘要： The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.
摘要翻译：公开了渐变钝化层的形成。在一个实施例中，一种方法包括四个步骤。在第一步骤中，提供半导体衬底上的至少一个晶体管。在第二步骤中，在至少一个晶体管上形成至少一个金属化层。在第三步骤中，氧化物层沉积在至少一个金属化层上。最后，在第四步骤中，施加预定掺杂剂的离子注入以在至少一个金属化层上产生渐变钝化膜。

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