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1. 发明授权

US5854115A Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length 失效
标题翻译：在晶体管栅极导体内形成蚀刻停止层以提供沟道长度的减小
公开(公告)号：US5854115A
公开(公告)日：1998-12-29
申请号：US979042
申请日：1997-11-26
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/518 , H01L21/28052 , H01L21/28176 , H01L21/823456 , H01L21/823828 , H01L21/82385 , H01L29/665 , H01L29/6659 , H01L29/66598 , Y10S438/97
摘要： A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.
摘要翻译：提供了一种用于形成晶体管栅极导体的工艺，该晶体管栅极导体具有布置在其上表面下方的深度处的蚀刻停止，使得蚀刻停止点之上的栅极导体的横向宽度可以专门变窄以提供晶体管沟道长度的减小。在栅极导体上形成图案的掩模层，即光致抗蚀剂被各向同性蚀刻，以便在蚀刻栅极导体之前将其横向宽度最小化。未被光致抗蚀剂保护的栅极导体的部分可以从蚀刻停止点的上方蚀刻，以限定用于栅极导体的上部的新的一对相对的侧壁表面。因此，栅极导体的上部的横向宽度可以减小到比常规栅极导体更小的尺寸。对栅极导体进行各向异性蚀刻，其中不被变窄的光致抗蚀剂保护的栅极导体的部分被蚀刻到蚀刻停止点。蚀刻停止的存在确保蚀刻停止的大部分和栅极导体的下面的部分在蚀刻完全终止之前不被去除。结果，多层栅极导体的下部比栅极导体的上部宽。

2. 发明授权

US6111298A Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length 有权
标题翻译：蚀刻停止层形成在多层栅极导体内以提供通道长度的减小
公开(公告)号：US6111298A
公开(公告)日：2000-08-29
申请号：US145010
申请日：1998-09-01
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/51 , H01L29/76
CPC分类号： H01L29/518 , H01L21/28052 , H01L21/28176 , H01L21/823456 , H01L21/823828 , H01L21/82385 , H01L29/665 , H01L29/6659 , H01L29/66598 , Y10S438/97
摘要： A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.
摘要翻译：提供了一种用于形成晶体管栅极导体的工艺，该晶体管栅极导体具有布置在其上表面下方的深度处的蚀刻停止，使得蚀刻停止点之上的栅极导体的横向宽度可以专门变窄以提供晶体管沟道长度的减小。在栅极导体上形成图案的掩模层，即光致抗蚀剂被各向同性蚀刻，以便在蚀刻栅极导体之前将其横向宽度最小化。未被光致抗蚀剂保护的栅极导体的部分可以从蚀刻停止点的上方蚀刻，以限定用于栅极导体的上部的新的一对相对的侧壁表面。因此，栅极导体的上部的横向宽度可以减小到比常规栅极导体更小的尺寸。对栅极导体进行各向异性蚀刻，其中不被变窄的光致抗蚀剂保护的栅极导体的部分被蚀刻到蚀刻停止点。蚀刻停止的存在确保蚀刻停止的大部分和栅极导体的下面的部分在蚀刻完全终止之前不被去除。结果，多层栅极导体的下部比栅极导体的上部宽。

3. 发明授权

US6077748A Advanced trench isolation fabrication scheme for precision polysilicon gate control 有权
标题翻译：高级沟槽隔离制造方案，用于精密多晶硅栅极控制
公开(公告)号：US6077748A
公开(公告)日：2000-06-20
申请号：US174898
申请日：1998-10-19
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/266 , H01L21/336 , H01L21/762 , H01L21/22
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/76237
摘要： An IGFET device isolation structure fabrication scheme includes the formation of electrically insulating isolation structures that extend into the substrate and extend above the surface of the substrate. The isolation structures are formed by providing a first mask to form trenches in the substrate. A layer of silicon dioxide is then deposited, filling the trenches and extending above the surface of the substrate. A second mask layer is formed. The second mask layer shadows the trench regions that were formed in the substrate. The silicon dioxide not shadowed by the second mask layer is removed, leaving isolation structures that extend both into the substrate and which rise above the substrate. A gate structure is formed in the region between two isolation structures, and, in the preferred embodiment, the gate structure extends above the substrate to the same height as the isolation structures. The isolation structures and the gate structure can be used to provide self-aligned doped source/drain regions. Spacers can be added to the isolation structure walls and the gate structure walls to provide heavily-doped self-aligned regions.
摘要翻译： IGFET器件隔离结构制造方案包括形成延伸到衬底中并延伸到衬底表面之上的电绝缘隔离结构。通过提供第一掩模以在衬底中形成沟槽来形成隔离结构。然后沉积一层二氧化硅，填充沟槽并在衬底的表面上方延伸。形成第二掩模层。第二掩模层阴影在衬底中形成的沟槽区域。除去未被第二掩模层遮蔽的二氧化硅，留下隔离结构，其延伸到衬底中并且在衬底上方上升。在两个隔离结构之间的区域中形成栅极结构，并且在优选实施例中，栅极结构在衬底上方延伸到与隔离结构相同的高度。隔离结构和栅极结构可用于提供自对准的掺杂源极/漏极区域。可以将间隔物添加到隔离结构壁和栅极结构壁以提供重掺杂的自对准区域。

4. 发明授权

US5959337A Air gap spacer formation for high performance MOSFETs 失效
标题翻译：用于高性能MOSFET的气隙间隔物形成
公开(公告)号：US5959337A
公开(公告)日：1999-09-28
申请号：US175193
申请日：1998-10-20
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/336 , H01L29/78 , H07L29/78
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/66598 , H01L29/7833
摘要： A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate. An interlevel dielectric is deposited to a level above the gate conductor across the semiconductor topography such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the gate conductor, and the interlevel dielectric is planarized to a level substantially coplanar with an upper surface of the masking structure. In an alternative embodiment, a refractory metal is deposited across an upper surface of the masking structure and across the source/drain implant areas subsequent to forming said source/drain implant areas. The refractory metal is heated to form a metal silicide overlying the source/drain implant areas and residual refractory metal is removed from above the masking structure. In yet another alternative embodiment, a single high-energy ion implant is used to simultaneously form the source/drain implant area and the lightly doped drain implant area following removal of select portions of the gate conductors.
摘要翻译：提供一种形成晶体管的方法，其中集成电路采用的栅极导体和相邻结构之间的电容耦合减小。根据实施例，栅极导体在半导体衬底之上介电间隔开，并且掩模结构布置在栅极导体的上表面上。执行与掩模结构的相对的侧向侧壁自对准的源极/漏极注入以在衬底内形成源极/漏极注入区域。选择栅极导体的部分被去除，使得掩模结构的相对端延伸超过栅极导体的相对的侧壁表面。执行与窄化栅极导体的相对侧壁表面自对准的轻掺杂漏极注入，以在衬底内形成轻掺杂的漏极注入区域。跨越半导体拓扑结构的层间电介质沉积到栅极导体上方的一个电平，使得气隙横向邻近栅极导体的相对的侧壁表面形成，并且层间电介质平坦化到基本上与平面的共面平面掩蔽结构。在替代实施例中，在形成所述源极/漏极注入区域之后，跨越掩模结构的上表面并横跨源极/漏极注入区域沉积难熔金属。难熔金属被加热以形成覆盖在源极/漏极注入区域上的金属硅化物，并且从掩蔽结构上方除去残留的难熔金属。在另一替代实施例中，在去除栅极导体的选择部分之后，单个高能离子注入用于同时形成源极/漏极注入区域和轻掺杂漏极注入区域。

5. 发明授权

US5869379A Method of forming air gap spacer for high performance MOSFETS' 失效
标题翻译：形成用于高性能MOSFET的气隙间隔物的方法
公开(公告)号：US5869379A
公开(公告)日：1999-02-09
申请号：US987116
申请日：1997-12-08
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/66598 , H01L29/7833
摘要： A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate. An interlevel dielectric is deposited to a level above the gate conductor across the semiconductor topography such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the gate conductor, and the interlevel dielectric is planarized to a level substantially coplanar with an upper surface of the masking structure. In an alternative embodiment, a refractory metal is deposited across an upper surface of the masking structure and across the source/drain implant areas subsequent to forming said source/drain implant areas. The refractory metal is heated to form a metal silicide overlying the source/drain implant areas and residual refractory metal is removed from above the masking structure. In yet another alternative embodiment, a single high-energy ion implant is used to simultaneously form the source/drain implant area and the lightly doped drain implant area following removal of select portions of the gate conductors.
摘要翻译：提供一种形成晶体管的方法，其中集成电路采用的栅极导体和相邻结构之间的电容耦合减小。根据实施例，栅极导体在半导体衬底之上介电间隔开，并且掩模结构布置在栅极导体的上表面上。执行与掩模结构的相对的侧向侧壁自对准的源极/漏极注入以在衬底内形成源极/漏极注入区域。选择栅极导体的部分被去除，使得掩模结构的相对端延伸超过栅极导体的相对的侧壁表面。执行与窄化栅极导体的相对侧壁表面自对准的轻掺杂漏极注入，以在衬底内形成轻掺杂的漏极注入区域。跨越半导体拓扑结构的层间电介质沉积到栅极导体上方的一个电平，使得气隙横向邻近栅极导体的相对的侧壁表面形成，并且层间电介质平坦化到基本上与平面的共面平面掩蔽结构。在替代实施例中，在形成所述源极/漏极注入区域之后，跨越掩模结构的上表面并横跨源极/漏极注入区域沉积难熔金属。难熔金属被加热以形成覆盖在源极/漏极注入区域上的金属硅化物，并且从掩蔽结构上方除去残留的难熔金属。在另一替代实施例中，在去除栅极导体的选择部分之后，单个高能离子注入用于同时形成源极/漏极注入区域和轻掺杂漏极注入区域。

6. 发明授权

US6069046A Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment 失效
标题翻译：晶体管制造采用将掺杂剂注入接点而不使栅极导体的侧壁表面进行离子轰击
公开(公告)号：US6069046A
公开(公告)日：2000-05-30
申请号：US979282
申请日：1997-11-26
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28123 , H01L21/823814 , H01L29/665
摘要： A process is provided for fabricating a transistor in which ion implantation of dopant into source/drain junctions is performed prior to defining the sidewall surfaces of a gate conductor. As such, the sidewall surfaces of the gate conductor are not subjected to damaging bombardment by ions. In one embodiment, a masking layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the masking layer is performed. Portions of the masking layer are removed to reduce the width of the masking layer and to form more closely spaced sidewalls. An LDD implant self-aligned to the new sidewalls of the masking layer is performed. Thereafter, the polysilicon layer is etched to define a gate conductor above and between LDD areas disposed within the substrate. In another embodiment, a sacrificial layer is patterned above a polysilicon layer dielectrically spaced above a semiconductor substrate. A S/D implant self-aligned to the sidewall surfaces of the sacrificial layer and an LDD implant self-aligned to exposed lateral edges of sidewall spacers arranged upon the sidewall surfaces of the sacrificial layer are performed. The polysilicon layer is then etched to define a gate conductor above and between LDD areas arranged within the substrate.
摘要翻译：提供了一种制造晶体管的工艺，其中在限定栅极导体的侧壁表面之前执行掺杂剂到源极/漏极结的离子注入。因此，栅极导体的侧壁表面不会受到离子的破坏性轰击。在一个实施例中，掩模层被图案化在介于半导体衬底之上的多晶硅层之上。执行与掩模层的侧壁表面自对准的S / D注入。去除掩模层的一部分以减小掩模层的宽度并形成更紧密间隔的侧壁。执行与掩模层的新侧壁自对准的LDD注入。此后，蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。在另一个实施例中，在半导体衬底上介电间隔的多晶硅层上方构图牺牲层。执行自对准到牺牲层的侧壁表面的S / D注入和与排列在牺牲层的侧壁表面上的侧壁间隔件的暴露的侧向边缘自对准的LDD注入。然后蚀刻多晶硅层以在布置在衬底内的LDD区域之上和之间限定栅极导体。

7. 发明授权

US5943562A Semiconductor fabrication employing a transistor gate coupled to a localized substrate 失效
标题翻译：使用耦合到局部衬底的晶体管栅极的半导体制造
公开(公告)号：US5943562A
公开(公告)日：1999-08-24
申请号：US949889
申请日：1997-10-14
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/8234 , H01L27/092 , H01L21/336 , H01L21/762
CPC分类号： H01L27/0922 , H01L21/823418
摘要： A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures. Dielectric spacers are formed upon the opposed sidewall surfaces of the gate conductor, and S/D regions are formed within the second substrate. The S/D implant is self-aligned to the exposed lateral edges of the dielectric spacers. The resulting transistor may be switched on quickly and has reduced current leakage in the off state. Transistors formed within and upon the first substrate are isolated from noise which may be induced in the second substrate.
摘要翻译：提供了一种用于形成晶体管的方法，其中栅极耦合到在第一衬底上介电间隔的第二衬底。根据一个实施例，跨越设置在单晶硅衬底上的插入介质层跨越形成多晶硅层。掺杂多晶硅层，使其成为第二半导体衬底。沟槽隔离结构可以在第二衬底内形成在随后的有效区域之间。在第二衬底上形成栅极氧化物，并且通过栅极氧化物蚀刻开口到第二衬底。导电材料形成在开口内，多晶硅沉积在栅极氧化物上。可以蚀刻多晶硅以在栅极氧化物上方形成栅极导体。 LDD注入区域形成在栅极导体和相邻隔离结构之间的第二衬底内。电介质间隔物形成在栅极导体的相对的侧壁表面上，并且S / D区形成在第二衬底内。 S / D植入物与介电间隔物的暴露的侧边缘自对准。所得到的晶体管可以快速接通并且在断开状态下具有减小的电流泄漏。在第一衬底内和之上形成的晶体管与可能在第二衬底中感应的噪声隔离。

8. 发明授权

US06300661B1 Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate 失效
标题翻译：用于将功率/接地施加到晶体管的源极和基底阱的相互注入区域
公开(公告)号：US06300661B1
公开(公告)日：2001-10-09
申请号：US09060509
申请日：1998-04-14
申请人： Daniel Kadosh , Mark I. Gardner , Michael P. Duane
发明人： Daniel Kadosh , Mark I. Gardner , Michael P. Duane
IPC分类号： H01L2976
CPC分类号： H01L21/823425 , H01L21/823493 , H01L27/088 , Y10S257/928
摘要： An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region. Also, merging a portion of the well-tie region with a portion of the source region affords increased packing density of an integrated circuit. The higher packing density is achieved without resorting to decreasing the dimensions of the well-tie region, and thus without detrimentally increasing the resistance of the well-tie region.
摘要翻译：提供了一种集成电路制造工艺，用于在阱内形成由位于阱内的晶体管的源极区域和耦合到阱的阱区域共享的阱内的相互注入区域，从而提供到该阱的单个电连接井和源区。触点可以耦合到相互植入区域，并且导体可以连接到触点。在阱是其中形成NMOS晶体管的p型阱的情况下，可以将接地电压施加到导体以偏置源极区域和阱。另一方面，如果阱是其中形成有PMOS晶体管的n型阱，则可以将电源电压VCC施加到导体以偏置源极区域和阱。不需要形成与源极区域和连接区域的接触以及与这些触点的导体的接触，所以需要较少的空间来偏置阱和源极区域。而且，将一部分连接区域与源区域的一部分合并，可以提高集成电路的堆积密度。填充密度更高，而不需要减小连接区域的尺寸，从而不会不利地增加连接区域的阻力。

9. 发明授权

US6040220A Asymmetrical transistor formed from a gate conductor of unequal thickness 失效
标题翻译：由不等厚度的栅极导体形成的非对称晶体管
公开(公告)号：US6040220A
公开(公告)日：2000-03-21
申请号：US950203
申请日：1997-10-14
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/78 , H01L21/00
CPC分类号： H01L29/66659 , H01L21/28114 , H01L21/823418 , H01L21/823456 , H01L29/42376 , H01L29/665 , H01L29/7835
摘要： An asymmetrical transistor, and a gate conductor used in forming that transistor, are provided. The gate conductor is formed by removing upper portions of the gate conductor along an elongated axis which the gate conductor extends. The removed portions presents a partially retained region of lesser thickness than the fully retained region immediately adjacent thereto. An implant is then forwarded to the substrate adjacent and partially below the gate conductor. Only the partially retained portions allow a subset of the originally forwarded ions to pass into the substrate to form a lightly doped drain (LDD) between the channel and the drain. The partially retained region occurs only near the drain and not adjacent the source so that the LDD area is self-aligned between the edge of the conductor and a line of demarcation separating the fully retained portion and the partially retained portion. There may be numerous lines of demarcation and corresponding numerous thicknesses across the gate conductor length to provide a graded LDD area if desired.
摘要翻译：提供了非对称晶体管和用于形成晶体管的栅极导体。通过沿着栅极导体延伸的细长轴去除栅极导体的上部而形成栅极导体。去除的部分呈现比其紧邻的完全保留区域更小的部分保留区域。然后将植入物在栅极导体附近和部分下方转移到衬底。只有部分保留的部分允许原始转移的离子的子集进入衬底，以在通道和漏极之间形成轻掺杂的漏极（LDD）。部分保留的区域仅在漏极附近发生并且不邻近源极，使得LDD区域在导体的边缘与分离完全保持部分和部分保持部分的分界线之间自对准。如果需要，跨栅极导体长度可以有许多分界线和对应的多个厚度以提供梯度的LDD面积。

10. 发明授权

US6030860A Elevated substrate formation and local interconnect integrated fabrication 失效
标题翻译：升高的基板形成和局部互连集成制造
公开(公告)号：US6030860A
公开(公告)日：2000-02-29
申请号：US993332
申请日：1997-12-19
申请人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
发明人： Mark I. Gardner , Daniel Kadosh , Michael P. Duane
IPC分类号： H01L21/768 , H01L21/822 , H01L27/06 , H01L21/00 , H01L21/8236
CPC分类号： H01L21/76895 , H01L21/8221 , H01L27/0688
摘要： A wafer includes levels elevated above the wafer substrate or base substrate which includes separated substrates suitable for circuit device element formation. In one embodiment, a first level dielectric is formed over circuit devices having elements formed in the wafer substrate. Contacts from the circuit elements may extend to the surface of the first level dielectric. A second dielectric is formed on the first level dielectric and etched to create separated openings with some openings exposing contacts. The openings are filled with substrate material, thus forming elevated substrates and local interconnects where exposed contact top surfaces are present. The substrate material is suitable for circuit device fabrication. Additional levels of elevated substrates and concurrently formed local interconnects may be subsequently fabricated.
摘要翻译：晶片包括在晶片衬底或基底衬底上方升高的层，其包括适于电路器件元件形成的分离的衬底。在一个实施例中，在具有在晶片衬底中形成的元件的电路器件上形成第一电平电介质。来自电路元件的触点可以延伸到第一级电介质的表面。在第一级电介质上形成第二电介质，并被蚀刻以产生具有露出触点的一些开口的分开的开口。开口填充有基底材料，从而形成凸起的基底和存在暴露的接触顶表面的局部互连。基板材料适用于电路器件制造。可以随后制造附加水平的升高的基底和同时形成的局部互连。

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