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91. 发明授权

US06323706B1 Apparatus and method for edge based duty cycle conversion 有权
标题翻译：基于边沿的占空比转换的装置和方法
公开(公告)号：US06323706B1
公开(公告)日：2001-11-27
申请号：US09513721
申请日：2000-02-24
申请人： Donald C. Stark , Stefanos Sidiropoulos
发明人： Donald C. Stark , Stefanos Sidiropoulos
IPC分类号： H03K3017
CPC分类号： H03K5/1534 , H03K5/151
摘要： A duty cycle converter generating a pair of output signals whose cross-point duty cycle is substantially equal to the edge duty cycle of a pair of input signals. The duty cycle converter includes an edge detector and a signal generator. The edge detector detects and indicates a first transition of a first input signal and a second transition of a second input signal. The signal generator takes the outputs of the edge detector and generates a first output signal and a second output signal. The signal generator causes the cross-point duty cycle of the first output signal to substantially equal the edge duty cycle of the first input cycle. The signal generator does so by forcing a first time delay between adjacent cross-over points of the first and second output signals to be substantially equal to a second time delay between the first transition and the second transition.
摘要翻译：产生一对输出信号的占空比转换器，其交叉点占空比基本上等于一对输入信号的边沿占空比。占空比转换器包括边缘检测器和信号发生器。边缘检测器检测并指示第一输入信号的第一转换和第二输入信号的第二转换。信号发生器接收边缘检测器的输出，并产生第一输出信号和第二输出信号。信号发生器使得第一输出信号的交叉点占空比基本上等于第一输入周期的边沿占空比。信号发生器通过强制第一和第二输出信号的相邻交叉点之间的第一时间延迟基本上等于第一转换和第二转换之间的第二时间延迟来实现。

92. 发明授权

US6122208A Circuit and method for column redundancy for high bandwidth memories 失效
标题翻译：高带宽存储器的列冗余电路和方法
公开(公告)号：US6122208A
公开(公告)日：2000-09-19
申请号：US398252
申请日：1999-09-17
申请人： Donald C. Stark
发明人： Donald C. Stark
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/70
摘要： A memory device includes a base memory with a defective memory cell. A read circuit with a serial output port and parallel input ports is connected to the base memory. The read circuit converts parallel read data received at the parallel input ports to a first serial data stream, which is applied to the serial output port. The first serial data stream includes a faulty bit corresponding to the defective memory cell. A spare memory stores a spare bit corresponding to the defective memory cell. A bit insertion circuit is connected to the spare memory and the serial output port of the read circuit. The bit insertion circuit substitutes the faulty bit value of the first serial data stream with the spare bit.
摘要翻译：存储器件包括具有缺陷存储器单元的基本存储器。具有串行输出端口和并行输入端口的读取电路连接到基本存储器。读取电路将并行输入端口处接收的并行读取数据转换为应用于串行输出端口的第一串行数据流。第一串行数据流包括对应于有缺陷的存储器单元的故障位。备用存储器存储对应于有缺陷的存储器单元的备用位。一个位插入电路连接到备用存储器和读取电路的串行输出端口。位插入电路用备用位代替第一串行数据流的故障位值。

93. 发明授权

US07535933B2 Calibrated data communication system and method 有权
标题翻译：校准数据通信系统及方法
公开(公告)号：US07535933B2
公开(公告)日：2009-05-19
申请号：US11327213
申请日：2006-01-05
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
摘要翻译：一种系统包括第一集成电路装置和第二集成电路装置。第一设备将数据序列发送到第二集成电路设备，并且第二设备对数据序列进行采样以产生接收机数据。然后，第二设备将接收机数据发送回第一设备。在第一集成电路装置内，执行数据序列与接收机数据之间的比较，并且基于比较，第一装置产生表示经校准的定时偏移的信息。第一设备使用代表校准的定时偏移的信息来调整与从第一集成电路向第二集成电路传送写入数据相关联的定时。

94. 发明授权

US07397725B2 Single-clock, strobeless signaling system 有权
标题翻译：单时钟，无频闪信号系统
公开(公告)号：US07397725B2
公开(公告)日：2008-07-08
申请号：US11320602
申请日：2005-12-30
申请人： Donald C. Stark
发明人： Donald C. Stark
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G06F13/4217 , G11C7/1072 , G11C7/22
摘要： A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
摘要翻译：信令系统包括信令路径，耦合到信令路径的主设备，耦合到信令路径的从设备和时钟发生器。从设备包括定时电路，用于产生具有相对于由时钟发生器提供的时钟信号的相位偏移的内部时钟信号，相位偏移至少部分地由信号路径上的信号传播时间确定。

95. 发明授权

US07091761B2 Impedance controlled output driver 有权
标题翻译：阻抗控制输出驱动
公开(公告)号：US07091761B2
公开(公告)日：2006-08-15
申请号：US11148783
申请日：2005-06-08
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： H03K5/12
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
摘要翻译：输出驱动器具有输出多路复用器和输出电流驱动器。输出多路复用器接收数据信号并输出q-节点信号。输出电流5河接收q节点信号，并根据q-节点信号驱动总线。输出多路复用器以各种方式处理数据信号以产生q-结点信号。输出电流驱动器响应于当前控制位以选择输出驱动电流的量。此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。

96. 发明授权

US06661268B2 Charge compensation control circuit and method for use with output driver 失效
公开(公告)号：US06661268B2
公开(公告)日：2003-12-09
申请号：US10014650
申请日：2001-12-11
申请人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
发明人： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC分类号： H03K512
CPC分类号： H03K17/164 , G11C7/1051 , H03K19/00384
摘要： An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

97. 发明授权

US5479370A Semiconductor memory with bypass circuit 失效
标题翻译：带旁路电路的半导体存储器
公开(公告)号：US5479370A
公开(公告)日：1995-12-26
申请号：US376439
申请日：1995-01-23
申请人： Tohru Furuyama , Donald C. Stark
发明人： Tohru Furuyama , Donald C. Stark
IPC分类号： G11C11/401 , G11C8/04 , G11C11/405 , G11C29/00 , G11C29/04 , G11C13/00 , G11C11/34
CPC分类号： G11C8/04
摘要： A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality of stages of shift circuits which is used as a serial address pointer for serially specifying the addresses of actually used rows and/or columns in the memory cell array, a bypass circuit capable of forming a bypass for the shift circuit at a given stage of the shift register, and a bypass control circuit for determining whether or not a bypass is to be formed by the bypass circuit.
摘要翻译：本发明的半导体存储器包括存储单元阵列，该存储单元阵列包含以矩阵形式布置的存储单元，每行连接到同一行中的所有存储单元的字线以及连接到同一列中的所有存储单元的位线，寄存器，其包含用于串行地指定存储单元阵列中的实际使用的行和/或列的地址的串行地址指针的多级移位电路，能够在一个位置上形成用于移位电路的旁路的旁路电路移位寄存器的给定级，以及用于判断旁路是否由旁路电路形成的旁路控制电路。

98. 发明授权

US5410512A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5410512A
公开(公告)日：1995-04-25
申请号：US64438
申请日：1993-05-21
申请人： Satoru Takase , Tohru Furuyama , Donald C. Stark , Natsuki Kushiyama , Kiyofumi Sakurai , Hiroyuki Noji , Shigeo Ohshima
发明人： Satoru Takase , Tohru Furuyama , Donald C. Stark , Natsuki Kushiyama , Kiyofumi Sakurai , Hiroyuki Noji , Shigeo Ohshima
IPC分类号： G11C11/401 , G06F12/02 , G11C7/00 , G11C7/10 , G11C11/407 , G11C11/41
CPC分类号： G11C7/1021
摘要： A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.
摘要翻译：半导体存储器件包括形成在芯片中的硅芯片和子阵列。在每个子阵列中，布置成矩阵形式的存储器单元，为每个子阵列的各行提供的字线，以及为每个子阵列的各列提供的位线。此外，在芯片中，放置用于放大从存储单元读出的数据的放大器组用于各个子阵列。连接到相应位线的放大器设置在放大器组中，并且放大器各自具有连续保持从存储单元读出的数据的功能。

99. 发明授权

US08630317B2 Memory system with calibrated data communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US08630317B2
公开(公告)日：2014-01-14
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

100. 发明授权

US07039147B2 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US07039147B2
公开(公告)日：2006-05-02
申请号：US10366865
申请日：2003-02-14
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H03D3/24
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.
摘要翻译：延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

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