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1. 发明授权

US5410512A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5410512A
公开(公告)日：1995-04-25
申请号：US64438
申请日：1993-05-21
申请人： Satoru Takase , Tohru Furuyama , Donald C. Stark , Natsuki Kushiyama , Kiyofumi Sakurai , Hiroyuki Noji , Shigeo Ohshima
发明人： Satoru Takase , Tohru Furuyama , Donald C. Stark , Natsuki Kushiyama , Kiyofumi Sakurai , Hiroyuki Noji , Shigeo Ohshima
IPC分类号： G11C11/401 , G06F12/02 , G11C7/00 , G11C7/10 , G11C11/407 , G11C11/41
CPC分类号： G11C7/1021
摘要： A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.
摘要翻译：半导体存储器件包括形成在芯片中的硅芯片和子阵列。在每个子阵列中，布置成矩阵形式的存储器单元，为每个子阵列的各行提供的字线，以及为每个子阵列的各列提供的位线。此外，在芯片中，放置用于放大从存储单元读出的数据的放大器组用于各个子阵列。连接到相应位线的放大器设置在放大器组中，并且放大器各自具有连续保持从存储单元读出的数据的功能。

2. 发明授权

US5341326A Semiconductor memory having memory cell units each including cascade-connected MOS transistors 失效
标题翻译：具有各自包括级联连接的MOS晶体管的存储单元单元的半导体存储器
公开(公告)号：US5341326A
公开(公告)日：1994-08-23
申请号：US833045
申请日：1992-02-10
申请人： Satoru Takase , Natsuki Kushiyama , Tohru Furuyama
发明人： Satoru Takase , Natsuki Kushiyama , Tohru Furuyama
IPC分类号： G11C11/405 , G11C11/56 , H01L21/8242 , H01L27/108 , G11C11/24 , G11C11/34
CPC分类号： G11C11/565
摘要： A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a first node, and a plurality of capacitors for data storage connected at one end to the MOS transistors, respectively at the end remote from the node, and there is a predetermined regulation in relation of the capacitance of the capacitors.
摘要翻译：半导体存储单元包括级联栅极，其包括多个级联连接的MOS晶体管，并且其一端连接到第一节点;以及多个用于数据存储的电容器，其一端连接到MOS晶体管，分别在远离节点，并且存在关于电容器的电容的预定调节。

3. 发明授权

US5532963A Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：US5532963A
公开(公告)日：1996-07-02
申请号：US523741
申请日：1995-09-05
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C29/02 , G11C29/24 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C11/401 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

4. 发明授权

US5377152A Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：US5377152A
公开(公告)日：1994-12-27
申请号：US978883
申请日：1992-11-19
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C29/02 , G11C29/24 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C11/401 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

5. 再颁专利

USRE37184E1 Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：USRE37184E1
公开(公告)日：2001-05-22
申请号：US09108266
申请日：1998-07-01
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C700
CPC分类号： G11C29/025 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

6. 发明授权

US5506540A Bias voltage generation circuit 失效
标题翻译：偏置电压发生电路
公开(公告)号：US5506540A
公开(公告)日：1996-04-09
申请号：US202082
申请日：1994-02-25
申请人： Kiyofumi Sakurai , Tohru Furuyama
发明人： Kiyofumi Sakurai , Tohru Furuyama
IPC分类号： G11C11/413 , G05F3/20 , G11C5/14 , G11C11/407 , G11C11/408 , H02M3/07 , G05F1/10 , G05F3/02
CPC分类号： G11C5/146 , G05F3/205
摘要： A bias voltage generation circuit has a bias voltage generation means and a VBB detector. The bias voltage generation means is made up of a charge pump circuit, and a ring oscillator for biasing a P-type region to have a predetermined potential level. The VBB detector detects the bias level of the P-type region and controls the bias generation means. The VBB detector incorporates a bias level detection circuit, and two delay circuits which are controlled on the basis of a signal appearing at an output node N2 of the bias level detection circuit. The ring oscillator is controlled on the basis of outputs of the two delay circuits. One of the two delay circuits has a higher detection level and is therefore less responsive to the signal at the output node N2 than the other delay circuit, but provides a shorter delay time than that provided by the other delay circuit.
摘要翻译：偏置电压产生电路具有偏置电压产生装置和VBB检测器。偏置电压产生装置由电荷泵电路和用于偏置P型区域以具有预定电位电平的环形振荡器构成。 VBB检测器检测P型区域的偏置电平并控制偏压产生装置。 VBB检测器包括偏置电平检测电路和两个基于出现在偏置电平检测电路的输出节点N2处的信号来控制的延迟电路。基于两个延迟电路的输出来控制环形振荡器。两个延迟电路中的一个具有较高的检测电平，因此对输出节点N2处的信号比另一个延迟电路响应较小，但是提供比另一延迟电路提供的延迟时间更短的延迟时间。

7. 发明授权

US5479370A Semiconductor memory with bypass circuit 失效
标题翻译：带旁路电路的半导体存储器
公开(公告)号：US5479370A
公开(公告)日：1995-12-26
申请号：US376439
申请日：1995-01-23
申请人： Tohru Furuyama , Donald C. Stark
发明人： Tohru Furuyama , Donald C. Stark
IPC分类号： G11C11/401 , G11C8/04 , G11C11/405 , G11C29/00 , G11C29/04 , G11C13/00 , G11C11/34
CPC分类号： G11C8/04
摘要： A semiconductor memory of this invention comprises a memory cell array containing memory cells arranged in matrix form, word lines each connected to all the memory cells in the same row, and bit lines each connected to all the memory cells in the same column, a shift register containing a plurality of stages of shift circuits which is used as a serial address pointer for serially specifying the addresses of actually used rows and/or columns in the memory cell array, a bypass circuit capable of forming a bypass for the shift circuit at a given stage of the shift register, and a bypass control circuit for determining whether or not a bypass is to be formed by the bypass circuit.
摘要翻译：本发明的半导体存储器包括存储单元阵列，该存储单元阵列包含以矩阵形式布置的存储单元，每行连接到同一行中的所有存储单元的字线以及连接到同一列中的所有存储单元的位线，寄存器，其包含用于串行地指定存储单元阵列中的实际使用的行和/或列的地址的串行地址指针的多级移位电路，能够在一个位置上形成用于移位电路的旁路的旁路电路移位寄存器的给定级，以及用于判断旁路是否由旁路电路形成的旁路控制电路。

8. 发明授权

US5265057A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5265057A
公开(公告)日：1993-11-23
申请号：US813510
申请日：1991-12-26
申请人： Tohru Furuyama , Hiroyuki Noji
发明人： Tohru Furuyama , Hiroyuki Noji
IPC分类号： H01L21/66 , G11C11/401 , G11C11/407 , G11C11/413 , G11C29/00 , G11C29/06 , G11C29/50 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C29/50 , G11C11/401
摘要： There is provided a semiconductor memory including a plurality of word lines, a plurality of bit lines intersecting the word lines, and a memory cell array having memory cells arranged at respective intersections of the word lines and bit lines. Word line selecting circuits select the word lines in accordance with an address signal and word line driving circuits are connected to the word lines for driving selected word lines. Selective stress applying circuitry selectively applies stress, during a stress test, to word lines in one of a plurality of word line groups into which all word lines are classified. The selective stress applying circuits includes an arrangement of MOS transistors and pads for applying stress to a word line group during the stress test.
摘要翻译：提供了包括多个字线，与字线相交的多个位线的半导体存储器，以及具有布置在字线和位线的各个交叉处的存储单元的存储单元阵列。字线选择电路根据地址信号选择字线，并且字线驱动电路连接到用于驱动所选字线的字线。选择应力施加电路在应力测试期间选择性地将应力施加到所有字线被分类到的多个字线组之一中的字线。选择应力施加电路包括在压力测试期间向字线组施加应力的MOS晶体管和焊盘的布置。

9. 发明授权

US5367481A Dynamic random access memory with complementary bit lines and capacitor common line 失效
标题翻译：具有互补位线和电容公共线的动态随机存取存储器
公开(公告)号：US5367481A
公开(公告)日：1994-11-22
申请号：US985114
申请日：1992-12-03
申请人： Satoru Takase , Tohru Furuyama
发明人： Satoru Takase , Tohru Furuyama
IPC分类号： G11C11/404 , G11C11/4074 , G11C11/409 , G11C11/24
CPC分类号： G11C11/4074
摘要： A DRAM comprising a memory cell array having a dynamic type memory cell having one MOS transistor for transfer gate and one capacitor for data storage with one end connected to the transistor, a word line connected in common to the gate of each transistor in each row of the memory cell array, a bit line connected in common to each transistor in each column of the memory cell array, a bit line precharge circuit provided so as to precharge the bit line of the memory cell array at a predetermined timing, a capacitor common line provided so as to correspond to a pair of complementary bit lines of the memory cell array and connected in common to the other end of the capacitor of the memory cell, a capacitor common precharge circuit provided so as to precharge the capacitor common line at predetermined timing, capacitor common line transfer gates for connecting the capacitor common line to the input nodes of a sense amplifier and on/off controlled at a predetermined timing, and bit line transfer gates for connecting the input nodes of the sense amplifier and the complementary pair of bit lines, respectively, and on/off controlled at a predetermined timing.
摘要翻译：一种DRAM，包括具有一个动态型存储单元的存储单元阵列，该存储单元具有一个用于传输门的MOS晶体管和一个用于数据存储的电容器，其一端连接到该晶体管，一个字线共同连接到每一行的每个晶体管的栅极存储单元阵列，与存储单元阵列的每列中的每个晶体管共同连接的位线，设置为预定时间对存储单元阵列的位线预充电的位线预充电电路，电容器公共线被设置为对应于存储单元阵列的一对互补位线并共同连接到存储单元的电容器的另一端;电容器公共预充电电路，被设置为以预定的时间对电容器公共线预充电用于将电容器公共线连接到读出放大器的输入节点的电容器公共线传输门和在预定定时控制的导通/截止，以及位线tran 用于分别连接读出放大器的输入节点和互补的一对比特线，以及在预定定时控制的开/关。

10. 发明授权

US5500815A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5500815A
公开(公告)日：1996-03-19
申请号：US981541
申请日：1992-11-25
申请人： Satoru Takase , Tohru Furuyama
发明人： Satoru Takase , Tohru Furuyama
IPC分类号： G11C11/401 , G11C11/404 , G11C11/405 , G11C11/56 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24 , G11C11/40
CPC分类号： G11C11/565 , G11C11/404 , H01L27/10805
摘要： A semiconductor memory cell comprises a first cascade gate, formed on a semiconductor substrate, having its end connected to a first node, and a plurality of MOS transistors which are connected in cascade, a plurality of data storage capacitors, formed on the semiconductor substrate, each of which has its end connected to that end of a corresponding one of the MOS transistors which is opposite to the first node, and a device isolation MOS transistor formed between the memory cell and another semiconductor memory cell which are arranged side by side on the semiconductor substrate.
摘要翻译：半导体存储单元包括形成在半导体衬底上的第一级联栅极，其端部连接到第一节点，以及串联连接的多个MOS晶体管，形成在半导体衬底上的多个数据存储电容器，其每个端部连接到与第一节点相对的相应的一个MOS晶体管的端部，以及形成在存储单元和另一半导体存储单元之间的器件隔离MOS晶体管，它们并排布置在半导体衬底。

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