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91. 发明申请

US20080108220A1 INTERCONNECT STRUCTURE WITH A BARRIER-REDUNDANCY FEATURE 有权
标题翻译：具有障碍 - 冗余特征的互连结构
公开(公告)号：US20080108220A1
公开(公告)日：2008-05-08
申请号：US11925161
申请日：2007-10-26
申请人： Chih-Chao Yang , Louis Hsu
发明人： Chih-Chao Yang , Louis Hsu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line. This electrical path generated by the inventive barrier-redundancy feature can avoid a sudden open circuit resulting from EM failure at the bottom of the via. The presence of the inventive barrier-redundancy feature within an interconnect structure provides sufficient time for chip replacement or system operation.
摘要翻译：提供一种互连结构，其包括能够在电迁移（EM）故障之后避免突然断路的障碍物冗余特征以及其形成方法。根据本发明，阻挡冗余特征位于互连结构内的预选位置，包括在宽线区域，细线区域或其任何组合中。阻挡层冗余特征包括导电材料，其位于导电线的导电线扩散阻挡层和上覆通孔的通孔扩散阻挡层之间并与之接触。本发明的阻挡 - 冗余特征的存在在沿着导电线的侧壁的通孔的侧壁和导电线扩散阻挡层之间形成通路扩散阻挡层之间的电路径。由本发明的障碍物冗余特征产生的该电路径可以避免由于通孔底部的EM故障导致的突然开路。在互连结构内部存在本发明的障碍物冗余特征为芯片更换或系统操作提供足够的时间。

92. 发明申请

US20080068038A1 Systems and Methods for Controlling of Electro-Migration 有权
公开(公告)号：US20080068038A1
公开(公告)日：2008-03-20
申请号：US11942241
申请日：2007-11-19
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.

93. 发明申请

US20080050890A1 HYBRID ORIENTED SUBSTRATES AND CRYSTAL IMPRINTING METHODS FOR FORMING SUCH HYBRID ORIENTED SUBSTRATES 失效
标题翻译：用于形成这种混合基板的混合基板和晶体印刷方法
公开(公告)号：US20080050890A1
公开(公告)日：2008-02-28
申请号：US11928456
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.
摘要翻译：一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。体硅区域各自定向为具有第三晶体取向。还提供了形成SOI区域和体硅区域的镶嵌或印刷方法。

94. 发明申请

US20080049378A1 METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US20080049378A1
公开(公告)日：2008-02-28
申请号：US11927774
申请日：2007-10-30
申请人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
发明人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
IPC分类号： H01G4/20
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少形成第一开口和至少第一绝缘层中的第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

95. 发明授权

US07329600B2 Low dielectric semiconductor device and process for fabricating the same 失效
标题翻译：低介电半导体器件及其制造方法
公开(公告)号：US07329600B2
公开(公告)日：2008-02-12
申请号：US10817179
申请日：2004-04-02
申请人： Lawrence Clevenger , Louis Hsu , Christy S. Tyberg , Tsorng-Dih Yuan
发明人： Lawrence Clevenger , Louis Hsu , Christy S. Tyberg , Tsorng-Dih Yuan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.
摘要翻译：一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

96. 发明申请

US20080034335A1 Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering 有权
标题翻译：结合具有减少的结电容和漏极诱导的阻挡层的半导体器件结构的设计结构
公开(公告)号：US20080034335A1
公开(公告)日：2008-02-07
申请号：US11875013
申请日：2007-10-19
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： G11C29/54
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：用于设计，制造或测试设计的机器可读介质中体现的设计结构。该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

97. 发明申请

US20080029841A1 STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING DIELECTRIC CHAMBER 审中-公开
标题翻译：用于形成电介质室的结构和方法以及包括电介质室的电子器件
公开(公告)号：US20080029841A1
公开(公告)日：2008-02-07
申请号：US11869958
申请日：2007-10-10
申请人： George Feng , Louis Hsu , Rajiv Joshi
发明人： George Feng , Louis Hsu , Rajiv Joshi
IPC分类号： H01L29/00
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.
摘要翻译：一种通过在半导体衬底上形成虚设结构而在电子器件上选择性地形成电介质室的方法（和结构），在虚拟结构上沉积介电层，通过介电层形成通向虚拟结构的开口，虚拟结构形成电介质室。

98. 发明申请

US20080014663A1 STRUCTURE AND METHOD OF FABRICATING A HINGE TYPE MEMS SWITCH 失效
标题翻译：铰链类型MEMS开关的结构和方法
公开(公告)号：US20080014663A1
公开(公告)日：2008-01-17
申请号：US11776835
申请日：2007-07-12
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang
IPC分类号： H01L21/00
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.
摘要翻译：描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 上下电极对; 并且由刚性可移动导电板连接和断开的上下互连布线。当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

99. 发明申请

US20070290345A1 STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS 失效
标题翻译：用于生产多个尺寸互连的结构和方法
公开(公告)号：US20070290345A1
公开(公告)日：2007-12-20
申请号：US11847776
申请日：2007-08-30
申请人： Lawrence Clevenger , Mukta Farooq , Louis Hsu , William Landers , Donna Zupanski-Nielsen , Carl Radens , Chih-Chao Yang
发明人： Lawrence Clevenger , Mukta Farooq , Louis Hsu , William Landers , Donna Zupanski-Nielsen , Carl Radens , Chih-Chao Yang
IPC分类号： H01L23/488 , H01L21/34
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/49 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/06102 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/49109 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , Y02P70/613 , H01L2224/29099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.
摘要翻译：一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。第一基板包括第一导电焊盘和第二导电焊盘。第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。第四导电焊盘包括与第一导电构件的高度不同的高度。导电构件电连接和机械地连接到第四导电垫。第一焊球将第一导电焊盘连接到第三导电焊盘。第一焊球包括第一直径。第二焊球将第二导电焊盘连接到第一导电构件。第二焊球包括第二直径。第一直径大于所述第二直径。

100. 发明申请

US20070281469A1 MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT 审中-公开
标题翻译：通过可靠性增强的底部结构进行修改
公开(公告)号：US20070281469A1
公开(公告)日：2007-12-06
申请号：US11839258
申请日：2007-08-15
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Conal Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Conal Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

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