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1. 发明申请

US20060267616A1 Systems and methods for controlling of electro-migration 有权
标题翻译：用于控制电迁移的系统和方法
公开(公告)号：US20060267616A1
公开(公告)日：2006-11-30
申请号：US11140765
申请日：2005-05-31
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

2. 发明申请

US20080068038A1 Systems and Methods for Controlling of Electro-Migration 有权
公开(公告)号：US20080068038A1
公开(公告)日：2008-03-20
申请号：US11942241
申请日：2007-11-19
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.

3. 发明申请

US20070164768A1 ON-CHIP ELECTROMIGRATION MONITORING SYSTEM 有权
标题翻译：片上电气监测系统
公开(公告)号：US20070164768A1
公开(公告)日：2007-07-19
申请号：US11306985
申请日：2006-01-18
申请人： Louis Hsu , Hayden Cranford , Oleg Gluschenkov , James Mason , Michael Sorna , Chih-Chao Yang
发明人： Louis Hsu , Hayden Cranford , Oleg Gluschenkov , James Mason , Michael Sorna , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.
摘要翻译：提供一种封装的半导体芯片，其包括半导体芯片和封装元件。半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间，将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时被监测元件的电阻超过阈值。

4. 发明申请

US20070103173A1 Systems and Methods for Controlling of Electro-Migration 有权
标题翻译：控制电迁移的系统和方法
公开(公告)号：US20070103173A1
公开(公告)日：2007-05-10
申请号：US11566796
申请日：2006-12-05
申请人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
发明人： Hayden Cranford , Louis Hsu , James Mason , Chih-Chao Yang
IPC分类号： G01R27/08
CPC分类号： G01R31/2858 , H01L21/76886 , H01L2924/0002 , H04B7/0814 , H01L2924/00
摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.
摘要翻译：公开了用于控制电迁移的系统和方法，并减少其有害影响。实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

5. 发明授权

US07657995B2 Method of fabricating a microelectromechanical system (MEMS) switch 失效
标题翻译：制造微机电系统（MEMS）开关的方法
公开(公告)号：US07657995B2
公开(公告)日：2010-02-09
申请号：US11776835
申请日：2007-07-12
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01H65/00
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
摘要翻译：一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

6. 发明申请

US20080079172A1 METHOD FOR FABRICATING AND BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS FORMATION OF HIGH-K AND LOW-K DIELECTRIC REGIONS 有权
标题翻译：同时形成高K和低K介电区域的制造和波形互连结构的方法
公开(公告)号：US20080079172A1
公开(公告)日：2008-04-03
申请号：US11939671
申请日：2007-11-14
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

7. 发明申请

US20080067608A1 Storage Elements with Disguised Configurations and Methods of Using the Same 审中-公开
标题翻译：具有伪装配置的存储元件及其使用方法
公开(公告)号：US20080067608A1
公开(公告)日：2008-03-20
申请号：US11928663
申请日：2007-10-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L27/06
CPC分类号： H01L23/585 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a first aspect, a first apparatus is provided. The first apparatus is an element of an integrated circuit (IC) having (1) a metal-oxide-semiconductor field-effect transistor (MOSFET) having source/drain diffusion regions; (2) an electrical fuse (eFuse) coupled to the MOSFET such that a portion of the eFuse serves as a gate region of the MOSFET; and (3) an implanted region coupled to the source/drain diffusion regions of the MOSFET such that a path between the source/drain diffusion regions functions as a short circuit or an open circuit. In another aspect, a design structure embodied in a machine readable medium for designing manufacturing, or testing a design is provided. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是具有（1）具有源极/漏极扩散区域的金属氧化物半导体场效应晶体管（MOSFET）的集成电路（IC）的元件; （2）耦合到所述MOSFET的电熔丝（eFuse），使得所述eFuse的一部分用作所述MOSFET的栅极区域; 和（3）耦合到MOSFET的源极/漏极扩散区域的注入区域，使得源极/漏极扩散区域之间的路径用作短路或开路。在另一方面，提供了体现在用于设计制造的机器可读介质或测试设计中的设计结构。提供了许多其他方面。

8. 发明申请

US20070278619A1 Semiconductor integrated circuit devices having high-Q wafer back-side capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US20070278619A1
公开(公告)日：2007-12-06
申请号：US11443394
申请日：2006-05-30
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

9. 发明申请

US20070211527A1 A REAL-TIME ADAPTIVE SRAM ARRAY FOR HIGH SEU IMMUNITY 有权
标题翻译：实时自适应SRAM阵列高SEU免疫
公开(公告)号：US20070211527A1
公开(公告)日：2007-09-13
申请号：US11308215
申请日：2006-03-13
申请人： Louis Hsu , Jack Mandelman , Robert Wong , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , Robert Wong , Chih-Chao Yang
IPC分类号： G11C16/04
CPC分类号： G11C11/4125
摘要： A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.
摘要翻译：一种用于自动调整存储器件（例如SRAM阵列）中的一个或多个电参数的系统和方法。该系统和方法实现SRAM感测子阵列，用于加速收集故障率数据，用于确定单个事件不起作息和主SRAM阵列性能之间的最佳权衡的操作点。将加速失败率数据输入到在电离粒子环境中将初级SRAM存储器阵列的SEU灵敏度设定为预定故障率的算法。为了提供符合最佳性能的SEU的免疫力，实时地维持预定的故障率。

10. 发明申请

US20070120218A1 CMOS compatible shallow-trench efuse structure and method 失效
标题翻译： CMOS兼容浅沟槽结构和方法
公开(公告)号：US20070120218A1
公开(公告)日：2007-05-31
申请号：US11290890
申请日：2005-11-30
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L21/268 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.
摘要翻译：提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。

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