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1. 发明授权

US07329600B2 Low dielectric semiconductor device and process for fabricating the same 失效
标题翻译：低介电半导体器件及其制造方法
公开(公告)号：US07329600B2
公开(公告)日：2008-02-12
申请号：US10817179
申请日：2004-04-02
申请人： Lawrence Clevenger , Louis Hsu , Christy S. Tyberg , Tsorng-Dih Yuan
发明人： Lawrence Clevenger , Louis Hsu , Christy S. Tyberg , Tsorng-Dih Yuan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.
摘要翻译：一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

2. 发明申请

US20050227480A1 Low dielectric semiconductor device and process for fabricating the same 失效
标题翻译：低介电半导体器件及其制造方法
公开(公告)号：US20050227480A1
公开(公告)日：2005-10-13
申请号：US10817179
申请日：2004-04-02
申请人： Lawrence Clevenger , Louis Hsu , Christy Tyberg , Tsorng-Dih Yuan
发明人： Lawrence Clevenger , Louis Hsu , Christy Tyberg , Tsorng-Dih Yuan
IPC分类号： H01L21/31 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.
摘要翻译：一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

3. 发明授权

US07657995B2 Method of fabricating a microelectromechanical system (MEMS) switch 失效
标题翻译：制造微机电系统（MEMS）开关的方法
公开(公告)号：US07657995B2
公开(公告)日：2010-02-09
申请号：US11776835
申请日：2007-07-12
申请人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Louis Hsu , Timothy Dalton , Lawrence Clevenger , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01H11/00 , H01H65/00
CPC分类号： H01H59/0009 , H01H1/20 , H01H2001/0084 , H01H2001/0089 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208
摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
摘要翻译：一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。导电板向上移动，使两条上部互连线路短路。相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

4. 发明申请

US20090312046A1 INTELLIGENT WIRELESS POWER CHARGING SYSTEM 有权
标题翻译：智能无线充电系统
公开(公告)号：US20090312046A1
公开(公告)日：2009-12-17
申请号：US12137185
申请日：2008-06-11
申请人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
发明人： Lawrence Clevenger , Timothy Dalton , Louis Hsu , Carl Radens
IPC分类号： H04B7/00 , H04M1/00
CPC分类号： H02J50/20 , H02J7/025 , H02J17/00
摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.
摘要翻译：一种用于无线网络设备智能电源管理的系统和方法。该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。电池通过嵌入在无线设备内部的射频收集单元进行充电。智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。第一个适配器设置为数据通信，而第二个适配器用于传输电源。此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

5. 发明申请

US20070278619A1 Semiconductor integrated circuit devices having high-Q wafer back-side capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US20070278619A1
公开(公告)日：2007-12-06
申请号：US11443394
申请日：2006-05-30
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

6. 发明申请

US20070040276A1 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US20070040276A1
公开(公告)日：2007-02-22
申请号：US11207218
申请日：2005-08-19
申请人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Nicholas Fuller , Louis Hsu
发明人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Nicholas Fuller , Louis Hsu
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

7. 发明申请

US20070023806A1 Method and structure for forming slot via bitline for MRAM devices 有权
标题翻译：用于通过MRAM器件的位线形成槽的方法和结构
公开(公告)号：US20070023806A1
公开(公告)日：2007-02-01
申请号：US11193660
申请日：2005-07-29
申请人： Michael Gaidis , Carl Radens , Lawrence Clevenger , Timothy Dalton , Louis Hsu , Keith Hon Wong , Chih-Chao Yang
发明人： Michael Gaidis , Carl Radens , Lawrence Clevenger , Timothy Dalton , Louis Hsu , Keith Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

8. 发明申请

US20060234443A1 MIM capacitor and method of fabricating same 有权
标题翻译： MIM电容器及其制造方法
公开(公告)号：US20060234443A1
公开(公告)日：2006-10-19
申请号：US11106887
申请日：2005-04-15
申请人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
发明人： Chih-Chao Yang , Lawrence Clevenger , Timothy Dalton , Louis Hsu
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.
摘要翻译：一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIN电容器包括具有顶表面和底表面的电介质层; 电介质层中的沟槽，沟槽从电介质层的顶表面延伸到底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫，沟槽的底部与电介质层的底表面共面; 绝缘层，形成在所述共形导电衬垫的顶表面上; 以及MIM电容器的第二板，其包括与所述绝缘层直接物理接触的芯导体，所述芯导体填充所述沟槽中的未被所述共形导电衬垫和所述绝缘层填充的空间。该方法包括与镶嵌互连线同时形成MIM电容器的部分。

9. 发明申请

US20060109117A1 Apparatus and Method of Intelligent Multistage System Deactivation 审中-公开
标题翻译：智能多级系统停用的装置与方法
公开(公告)号：US20060109117A1
公开(公告)日：2006-05-25
申请号：US10904664
申请日：2004-11-22
申请人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
发明人： Louis Hsu , Lawrence Clevenger , Carl Radens , Kwong Wong , Chih-Chao Yang , Timothy Dalton
IPC分类号： G08B13/14
CPC分类号： G06F21/554 , G06F21/81 , G06F21/86
摘要： A deactivation management unit for facilitating an intelligent multistage system deactivation process where the deactivation management unit is flexible, facilitates recovery, and renders reverse engineering nearly impossible after the system has been permanently deactivated.
摘要翻译：一种停用管理单元，用于促进智能多级系统停用过程，其中停用管理单元是灵活的，便于恢复，并且在系统被永久停用之后几乎不可能实现逆向工程。

10. 发明申请

US20090111235A1 Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US20090111235A1
公开(公告)日：2009-04-30
申请号：US12348707
申请日：2009-01-05
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/02
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

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