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91. 发明申请

US20050205522A1 Chemical agent additives in copper CMP slurry 审中-公开
标题翻译：铜CMP浆料中的化学添加剂
公开(公告)号：US20050205522A1
公开(公告)日：2005-09-22
申请号：US11130377
申请日：2005-05-16
申请人： Paul Ho , Mei Zhou , Chockalingam Ramasamy
发明人： Paul Ho , Mei Zhou , Chockalingam Ramasamy
IPC分类号： B44C1/22 , C09G1/02 , C23F1/00 , C23F3/06
CPC分类号： C09G1/02 , C23F3/06
摘要： A polishing method is achieved comprising the following steps. A layer made of material containing a metal as a main component over a substrate having recessed portions on a surface thereof so as to fill the recessed portions with the metal layer is formed. The metal is Cu, a Cu alloy, Al, or an Al alloy. The metal layer is polished by a chemical mechanical polishing method using a slurry including a polishing agent. The polishing agent contains a chemical agent and an etching agent. The chemical agent includes at least a carbonyl derivative of benzotriazole and is responsible for forming a protective film on the surface of the metal layer by reacting with the material containing a metal as a main component. The etching agent is responsible for etching the material containing a metal as a main component.
摘要翻译：实现了以下步骤的抛光方法。形成由含有金属作为主要成分的材料制成的层，该基材在其表面上具有凹陷部分的基底上，以便用金属层填充凹陷部分。金属是Cu，Cu合金，Al或Al合金。通过使用包括抛光剂的浆料的化学机械抛光方法对金属层进行抛光。抛光剂含有化学试剂和蚀刻剂。化学试剂至少包括苯并三唑的羰基衍生物，并且负责通过与含有金属作为主要成分的材料反应在金属层的表面上形成保护膜。蚀刻剂负责蚀刻含有金属作为主要成分的材料。

92. 发明申请

US20050196931A1 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US20050196931A1
公开(公告)日：2005-09-08
申请号：US11123748
申请日：2005-05-04
申请人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
发明人： Jian Li , Lap Chan , Purakh Verma , Jia Zheng , Shao-fu Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

93. 发明申请

US20050191851A1 Barrier metal cap structure on copper lines and vias 审中-公开
标题翻译：铜线和通孔上的金属盖结构
公开(公告)号：US20050191851A1
公开(公告)日：2005-09-01
申请号：US11119274
申请日：2005-04-29
申请人： Wuping Liu , Beichao Zhang , Liang Hsia
发明人： Wuping Liu , Beichao Zhang , Liang Hsia
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76807 , H01L21/7684 , H01L21/76865 , H01L21/76877
摘要： A new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation of a cap of barrier material, conventional concerns of copper oxidation, copper back-sputtering and the like are eliminated.
摘要翻译：提供了一种用于创建镶嵌铜互连的新方法。提供了一种方法，由此产生的铜表面被一层屏障材料盖住。通过阻挡材料的盖结构，所制造的铜互连的表面被屏蔽以防止诸如加工化学品的影响等外部影响。作为阻挡材料盖的形成的结果，消除了铜氧化，铜背溅射等的常规问题。

94. 发明申请

US20050184295A1 Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication 有权
标题翻译：用于双重镶嵌制造中Cu阻挡层和蚀刻停止层的氧掺杂SiC
公开(公告)号：US20050184295A1
公开(公告)日：2005-08-25
申请号：US10785520
申请日：2004-02-24
申请人： Liu Huang , John Sudijono , Koh Wee
发明人： Liu Huang , John Sudijono , Koh Wee
IPC分类号： H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially depositing a first dielectric layer, a second oxygen doped SiC etch stop layer, and a second dielectric layer. A via and overlying trench are formed and filled with a diffusion barrier layer and a metal layer. The oxygen doped SiC layers have a lower dielectric constant than SiC or SIGN and a higher breakdown field than SiC. The etch selectivity of a C4F8/Ar etch for a SiCOH layer relative to the oxygen doped SiC layer is at least 6:1 because of a lower oxygen content in the oxygen doped SiC layer.
摘要翻译：描述了一种形成具有改进性能的双镶嵌结构的方法。由氧掺杂的SiC构成的第一蚀刻停止层沉积在SiC阻挡层上，以在衬底上形成复合势垒/蚀刻停止层。镶嵌层的剩余部分通过依次沉积第一介电层，第二氧掺杂的SiC蚀刻停止层和第二介电层而形成。形成通孔和上覆沟槽并填充有扩散阻挡层和金属层。氧掺杂的SiC层具有比SiC或SIGN更低的介电常数和比SiC更高的击穿场。对于SiCOH层，相对于氧掺杂的SiC层，C 4 Si 8 N / Ar蚀刻的蚀刻选择性为至少6:1，因为氧含量低氧掺杂的SiC层。

95. 发明授权

US06933188B1 Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies 失效
标题翻译：使用选择性硬掩模在深亚微米制造技术中集成双扩散漏极MOS器件
公开(公告)号：US06933188B1
公开(公告)日：2005-08-23
申请号：US10858024
申请日：2004-06-01
申请人： Purakh Raj Verma , Sanford Chu , Hwee Ngoh Chua
发明人： Purakh Raj Verma , Sanford Chu , Hwee Ngoh Chua
IPC分类号： H01L21/324 , H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/66575 , H01L21/324 , H01L21/823814
摘要： A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an insulator hard mask shape on an underlying polysilicon gate structure shape in the DDD MOSFET region, while only a polysilicon gate structure shape is formed in the CMOS device region. High energy ion implantation procedures are employed to form the deep source/drain regions of the DDD MOSFET devices with the insulator hard mask shape preventing the high energy implantation procedure from disturbing the underlying channel region. An anneal procedure used activate and drive—in the implanted ions in the deep source/drain region of the DDD MOSFET device is followed by formation of the shallower source/drain regions of the sub-micron CMOS devices.
摘要翻译：已经开发了将双扩散漏极（DDD）MOSFET器件制造与制造亚微米CMOS器件集成的过程。该工艺特征是在DDD MOSFET区域中形成底层多晶硅栅极结构形状的绝缘体硬掩模形状，而在CMOS器件区域中仅形成多晶硅栅极结构形状。采用高能离子注入方法形成具有绝缘体硬掩模形状的DDD MOSFET器件的深源极/漏极区域，从而防止高能量注入过程扰乱下面的沟道区域。在DDD MOSFET器件的深源极/漏极区域激活并驱动注入离子的退火程序之后，形成亚微米CMOS器件的较浅的源极/漏极区域。

96. 发明申请

US20050167824A1 Integrated circuit with protective moat 有权
标题翻译：集成电路与防护护城河
公开(公告)号：US20050167824A1
公开(公告)日：2005-08-04
申请号：US10768796
申请日：2004-01-30
申请人： Fan Zhang , Kho Chok , Tae Lee , Xiaomei Bu , Meng Luo , Chian Sin , Yee Foong , Luona Goh , Liang Hsia , Huey Chong
发明人： Fan Zhang , Kho Chok , Tae Lee , Xiaomei Bu , Meng Luo , Chian Sin , Yee Foong , Luona Goh , Liang Hsia , Huey Chong
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L23/04 , H01L23/31 , H01L23/58 , H01L27/04
CPC分类号： H01L23/585 , H01L23/3192 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.
摘要翻译：制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。形成与金属线连接的接合焊盘。通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。

97. 发明授权

US06924180B2 Method of forming a pocket implant region after formation of composite insulator spacers 有权
标题翻译：在形成复合绝缘垫片之后形成凹穴注入区域的方法
公开(公告)号：US06924180B2
公开(公告)日：2005-08-02
申请号：US10361934
申请日：2003-02-10
申请人： Elgin Quek
发明人： Elgin Quek
IPC分类号： H01L21/336 , H01L29/78 , H01L21/84
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconductor substrate not covered by the gate structure or by composite insulator spacers located on the sides of the gate structure. Selective removal of an overlying insulator component of the composite insulator spacer allows a subsequent pocket implant region to be formed in an area of the semiconductor substrate directly underlying a horizontal portion of a remaining L shaped insulator spacer component. The location of the pocket region, formed butting only the top portions of the sides of the heavily doped source/drain region, reduces the risk of punch through current while limiting the impact of junction capacitance.
摘要翻译：已经开发了用于形成MOSFET器件的工艺，其特征在于仅与重掺杂源极/漏极区域的侧面的顶部附近放置的口袋区域。该工艺的特征是在未被栅极结构覆盖的半导体衬底的区域中或通过位于栅极结构的侧面上的复合绝缘体间隔物形成重掺杂的源极/漏极区域。选择性去除复合绝缘体间隔物的上覆绝缘体部件允许随后的口袋注入区域形成在半导体衬底的直接位于剩余的L形绝缘体间隔件部件的水平部分下方的区域中。仅在重掺杂的源极/漏极区域形成对接的顶部的袋区域的位置降低穿通电流的风险，同时限制结电容的冲击。

98. 发明申请

US20050164436A1 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US20050164436A1
公开(公告)日：2005-07-28
申请号：US10865433
申请日：2004-06-10
申请人： Jin Liu , Dong Sohn , Liang Hsia
发明人： Jin Liu , Dong Sohn , Liang Hsia
IPC分类号： C30B29/52 , H01L21/20 , H01L29/10 , H01L21/338 , C30B1/00 , H01L21/36
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054
摘要： A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent, overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses. In situ growth of an overlying silicon—germanium layer featuring uniform or non—graded germanium content, results in a relaxed silicon—germanium layer with a minimum of dislocations propagating from the underlying graded silicon—germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

99. 发明申请

US20050162153A1 Zero-temperature-gradient zero-bias thermally stimulated current technique to characterize defects in semiconductors or insulators 有权
公开(公告)号：US20050162153A1
公开(公告)日：2005-07-28
申请号：US11083187
申请日：2005-03-17
申请人： Wai Lau
发明人： Wai Lau
IPC分类号： G01R31/12 , H01L21/00 , H01L31/058
CPC分类号： H01L21/67288 , G01R31/12 , H01L21/67248
摘要： A process for characterizing defects in semiconductors or insulators using a zero-bias thermally stimulated current technique wherein parasitic current is eliminated by the use of a novel ZBTSC apparatus that eliminates temperature gradient across a sample is described. The novel ZBTSC apparatus comprises a cold finger on a cyrostat. A sample holder is attached to the cold finger. A probe holder is attached to the cold finger. A probe is attached to the probe holder. A feedback temperature control keeps the probe and the cold finger at the same temperature. Alternatively, the sample holder may be attached to a first cold finger and the probe holder attached to a second cold finger. Feedback temperature controls for each cold finger are programed such that their temperatures are kept the same. The improved zero-bias thermally stimulated current technique of the invention comprises mounting a sample on the sample holder of the novel ZBTSC apparatus. The sample is excited at a first temperature to fill up defect traps with carriers and then heated to a second temperature higher than the first temperature wherein the heating is a linear function with respect to time. Defects are characterized by measuring current due to emission of the carriers from the defect traps as a function of temperature wherein the measuring is performed by the probe of the novel ZBTSC apparatus.

100. 发明申请

US20050153495A1 Silicon - germanium virtual substrate and method of fabricating the same 有权
标题翻译：硅 - 锗虚拟衬底及其制造方法
公开(公告)号：US20050153495A1
公开(公告)日：2005-07-14
申请号：US10755501
申请日：2004-01-12
申请人： Jin Liu
发明人： Jin Liu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/78 , H01L29/1054
摘要： A method of forming a relaxed silicon-germanium layer for accommodation of an overlying silicon layer formed with tensile strain, has been developed. The method features growth of multiple composite layers on a semiconductor substrate, with each composite layer comprised of an underlying silicon-germanium-carbon layer and of an overlying silicon-germanium layer, followed by the growth of an overlying thicker silicon-germanium layer. A hydrogen anneal procedure performed after growth of the multiple composite layers and of the thicker silicon-germanium layer, results in a top composite layer now comprised with an overlying relaxed silicon-germanium layer, exhibiting a low dislocation density. The presence of silicon-carbon micro crystals in each silicon-germanium-carbon layer reduces the formation of, and the propagation of threading dislocations in overlying silicon-germanium layers, therefore also reducing extension of these defects into an overlying silicon layer, wherein the tensile strained silicon layer will be used to accommodate a subsequent device structure.
摘要翻译：已经开发了形成用于容纳形成有拉伸应变的上覆硅层的松弛硅 - 锗层的方法。该方法的特征是在半导体衬底上生长多个复合层，其中每个复合层由下面的硅 - 锗 - 碳层和上覆的硅 - 锗层组成，随后生长上覆的较厚的硅 - 锗层。在多个复合层和更厚的硅 - 锗层的生长之后执行的氢退火程序导致顶层复合层现在包含具有低位错密度的上覆松弛硅 - 锗层。在每个硅 - 锗 - 碳层中硅 - 碳微晶的存在减少了覆盖硅 - 锗层中穿透位错的形成和扩散，因此也减少了这些缺陷扩展到上覆硅层，其中拉伸应变硅层将用于适应随后的器件结构。

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