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1. 发明申请

US20070149160A1 FREQUENCY CONVERSION IN A RECEIVER 审中-公开
标题翻译：接收器中的频率转换
公开(公告)号：US20070149160A1
公开(公告)日：2007-06-28
申请号：US11675656
申请日：2007-02-16
申请人： Chaowen Tseng , Wai Lau
发明人： Chaowen Tseng , Wai Lau
IPC分类号： H04B1/26 , H04B15/00
CPC分类号： H03L7/18 , H03D7/161 , H03L2207/10 , H04B1/28
摘要： A method for frequency conversion in a receiver. A signal having a radio frequency and carrying information on a selected channel is received and converted from the radio frequency to a first variable intermediate frequency determined by the selected channel. The signal is further converted from the first variable intermediate frequency to a second variable intermediate frequency determined by the selected channel. The signal is further converted from the second variable intermediate frequency to a constant baseband frequency.
摘要翻译：一种用于接收机中的频率转换的方法。接收具有射频并携带所选信道上的信息的信号，并将其从射频转换为由所选频道确定的第一可变中频。信号进一步从第一可变中频转换成由所选频道确定的第二可变中频。信号进一步从第二可变中频转换成恒定的基带频率。

2. 发明申请

US20050162153A1 Zero-temperature-gradient zero-bias thermally stimulated current technique to characterize defects in semiconductors or insulators 有权
公开(公告)号：US20050162153A1
公开(公告)日：2005-07-28
申请号：US11083187
申请日：2005-03-17
申请人： Wai Lau
发明人： Wai Lau
IPC分类号： G01R31/12 , H01L21/00 , H01L31/058
CPC分类号： H01L21/67288 , G01R31/12 , H01L21/67248
摘要： A process for characterizing defects in semiconductors or insulators using a zero-bias thermally stimulated current technique wherein parasitic current is eliminated by the use of a novel ZBTSC apparatus that eliminates temperature gradient across a sample is described. The novel ZBTSC apparatus comprises a cold finger on a cyrostat. A sample holder is attached to the cold finger. A probe holder is attached to the cold finger. A probe is attached to the probe holder. A feedback temperature control keeps the probe and the cold finger at the same temperature. Alternatively, the sample holder may be attached to a first cold finger and the probe holder attached to a second cold finger. Feedback temperature controls for each cold finger are programed such that their temperatures are kept the same. The improved zero-bias thermally stimulated current technique of the invention comprises mounting a sample on the sample holder of the novel ZBTSC apparatus. The sample is excited at a first temperature to fill up defect traps with carriers and then heated to a second temperature higher than the first temperature wherein the heating is a linear function with respect to time. Defects are characterized by measuring current due to emission of the carriers from the defect traps as a function of temperature wherein the measuring is performed by the probe of the novel ZBTSC apparatus.

3. 发明授权

US06859083B1 Circuits for reducing leakage currents in pull-up and pull-down circuits using very small MOSFET devices 有权
标题翻译：使用非常小的MOSFET器件减少上拉和下拉电路中的漏电流的电路
公开(公告)号：US06859083B1
公开(公告)日：2005-02-22
申请号：US10630322
申请日：2003-07-30
申请人： Jane Xin-LeBlanc , Wai Lau
发明人： Jane Xin-LeBlanc , Wai Lau
IPC分类号： H03L7/089 , H03L5/00
CPC分类号： H03L7/0891
摘要： A pull-down circuit for pulling a high-impedance node to ground when a pull-down (PD) signal driving the pull-down circuit is Logic 1. The pull-down circuit comprises: 1) a first pull-down N-channel transistor having a drain coupled to the high-impedance node, a gate coupled to the PD signal, and a source coupled to a common node; 2) a second pull-down N-channel transistor having a drain coupled to the common node, a gate coupled to the PD signal, and a source coupled to a ground rail;, wherein the first and second pull-down N-channel transistors are off when the PD signal is Logic 0 and are on when the PD signal is Logic 1; and 3) a gate-biasing circuit driven by the PD signal. The gate-biasing circuit is off when the PD signal is Logic 1 and the gate-biasing circuit applies a Logic 1 bias voltage to the common node when the PD signal is Logic 0. The Logic 1 bias voltage creates a negative Vgs bias on the first pull-down N-channel transistor when the PD signal is Logic 0. An analogous pull-up circuit also is disclosed.
摘要翻译：当驱动下拉电路的下拉（PD）信号是逻辑1时，用于将高阻抗节点拉到地的下拉电路。下拉电路包括：1）第一下拉N沟道晶体管具有耦合到高阻抗节点的漏极，耦合到PD信号的栅极和耦合到公共节点的源极; 2）具有耦合到所述公共节点的漏极的第二下拉N沟道晶体管，耦合到所述PD信号的栅极和耦合到接地轨的源极;其中所述第一和第二下拉N沟道晶体管当PD信号为逻辑0时为OFF，当PD信号为逻辑1时为ON; 和3）由PD信号驱动的栅极偏置电路。当PD信号为逻辑1时，栅极偏置电路关闭，当PD信号为逻辑0时，栅极偏置电路向公共节点施加逻辑1偏置电压。逻辑1偏置电压在当PD信号为逻辑0时，第一下拉式N沟道晶体管也是公开了类似的上拉电路。

4. 发明申请

US20070055534A1 Method and system for implementing advertising and marketing campaign in electronic and computer devices 审中-公开
标题翻译：在电子和计算机设备中实施广告和营销活动的方法和系统
公开(公告)号：US20070055534A1
公开(公告)日：2007-03-08
申请号：US11209296
申请日：2005-08-24
申请人： Wai Lau
发明人： Wai Lau
IPC分类号： G06Q99/00
CPC分类号： G06Q30/02
摘要： The invention is a advertising and marketing system relates to method and system to implement advertising and marketing campaign by delivering advertising and marketing message in electronic and computer devices. It integrates with the applications of the electronic and computer devices and applies algorithms to assign routing paths for message delivery. It comprises of three sub-systems and one side-system. The condition sub-system assesses the defined conditions and uses user choice algorithm, one-to-one simple algorithm, one-to-multiple complex algorithm and semi-complex algorithm as logistic to assign routing path. Alert side-system is running in condition sub-system level to persuade user to look for defined conditions. Following is the response sub-system to display the message with special effect to improve attractiveness of the message. Reinforcement sub-system is for enhancing the power of influence of message to the user.
摘要翻译：本发明涉及通过在电子和计算机设备中提供广告和营销消息来实现广告和营销活动的方法和系统的广告和营销系统。它与电子和计算机设备的应用集成，并应用算法来分配消息传递的路由路径。它由三个子系统和一个侧系统组成。条件子系统评估定义的条件，并使用用户选择算法，一对一简单算法，一对多复杂算法和半复杂算法作为逻辑来分配路由路径。警报侧系统在条件子系统级别运行，以说服用户查找定义的条件。以下是响应子系统显示消息的特殊效果，以提高消息的吸引力。加固子系统是为了增强消息对用户的影响力。

5. 发明申请

US20050164662A1 Frequency conversion in a receiver 审中-公开
标题翻译：接收机中的频率转换
公开(公告)号：US20050164662A1
公开(公告)日：2005-07-28
申请号：US10762455
申请日：2004-01-23
申请人： Chaowen Tseng , Wai Lau
发明人： Chaowen Tseng , Wai Lau
IPC分类号： H04N5/44 , H03D7/16 , H03L7/18 , H04B1/00 , H04B1/28
CPC分类号： H03L7/18 , H03D7/161 , H03L2207/10 , H04B1/28
摘要： A method for frequency conversion of a receiver, including the steps of receiving a signal having a radio frequency and carrying information on a plurality of channels, selecting one of the channels, converting the signal from the radio frequency to a first variable frequency determined by the selected channel, and converting the signal from the first frequency to a desired frequency.
摘要翻译：一种用于接收机频率变换的方法，包括以下步骤：接收具有射频的信号并在多个信道上携带信息，选择一个信道，将来自射频的信号转换成由第并将信号从第一频率转换成期望的频率。

6. 发明授权

US06262610B1 Voltage sample and hold circuit for low leakage charge pump 有权
标题翻译：低泄漏电荷泵的电压采样和保持电路
公开(公告)号：US06262610B1
公开(公告)日：2001-07-17
申请号：US09383162
申请日：1999-08-25
申请人： Steve Lo , Christian Olgaard , Wai Lau
发明人： Steve Lo , Christian Olgaard , Wai Lau
IPC分类号： G11C2702
CPC分类号： H03L7/0895 , G11C27/026
摘要： A voltage sample and hold circuit for use as part of a low leakage charge pump circuit in a phase lock loop (PLL). During an inactive state of the charge pumping function, a MOSFET switch that normally connects the charge pump output to the loop filter preceding the voltage controlled oscillator (VCO) of the PLL is opened, e.g., for open loop modulation of the VCO. Meanwhile, the sample and hold circuit which has sampled the voltage at the input side of the MOSFET switch now maintains that voltage, thereby forcing a zero-voltage difference across the MOSFET switch. This zero-voltage difference virtually eliminates subthreshold leakage current through the MOSFET switch, thereby significantly reducing loss of charge in the loop filter due to such leakage current. This ensures a significantly more constant DC bias at the input to the VCO and, therefore, a more stable output center, or carrier, frequency from the PLL during open loop modulation.
摘要翻译：一个电压采样和保持电路，用作锁相环（PLL）中低泄漏电荷泵电路的一部分。在电荷泵浦功能的无效状态期间，通常将电荷泵输出连接到PLL的压控振荡器（VCO）之前的环路滤波器的MOSFET开关被打开，例如用于VCO的开环调制。同时，对MOSFET开关输入侧的电压进行采样的采样保持电路现在保持该电压，从而迫使MOSFET开关之间产生零电压差。该零电压差实际上消除了通过MOSFET开关的亚阈值漏电流，从而显着减少了由于这种漏电流导致的环路滤波器中的电荷损失。这确保了在VCO的输入处的显着更恒定的DC偏置，因此在开环调制期间来自PLL的更稳定的输出中心或载波频率。

7. 发明申请

US20070112567A1 Techiques for model optimization for statistical pattern recognition 审中-公开
标题翻译：用于统计模式识别的模型优化技术
公开(公告)号：US20070112567A1
公开(公告)日：2007-05-17
申请号：US11594717
申请日：2006-11-07
申请人： Wai Lau , Steven Lee
发明人： Wai Lau , Steven Lee
IPC分类号： G10L15/00
CPC分类号： G06K9/72 , G06Q30/02 , G06Q30/0207 , G06Q30/0247 , G06Q30/0252 , G06Q30/0255 , G06Q30/0261 , G06Q30/0264 , G06Q30/0269 , G06Q30/0275 , G10L15/06
摘要： In one embodiment, a statistical pattern recognition engine determines content for a statistical pattern recognition task. The content and/or information related to the content is analyzed to determine a model to use in the statistical pattern recognition. For example, models may be classified in a plurality of domains based on different sets of data used to train models in the domain. The models may be classified based on knowledge sources used to generate the models, such as a news knowledge source, entertainment knowledge source, business knowledge source, etc. A model in the plurality of models is then determined based on the analysis where the determined model is classified in a domain. The model is then used by the statistical pattern recognition engine to perform the statistical pattern recognition task. For example, spoken words are transcribed into text using the determined model.
摘要翻译：在一个实施例中，统计模式识别引擎确定统计模式识别任务的内容。分析与内容相关的内容和/或信息，以确定在统计模式识别中使用的模型。例如，基于用于训练域中的模型的不同的数据集，模型可以被分类在多个域中。模型可以基于用于生成模型的知识来源，例如新闻知识源，娱乐知识源，商业知识源等。然后基于所确定的模型的分析来确定多个模型中的模型被归类到一个域中。然后，该模型由统计模式识别引擎用于执行统计模式识别任务。例如，使用确定的模型将口语单词转录成文本。

8. 发明申请

US20070105514A1 Low Noise, High Linearity TV Tuner Architecture with Switched Fixed-Gain LNA 审中-公开
标题翻译：低噪声，高线性电视调谐器结构，带开关固定增益LNA
公开(公告)号：US20070105514A1
公开(公告)日：2007-05-10
申请号：US11423455
申请日：2006-06-12
申请人： Chao-Wen Tseng , Wai Lau
发明人： Chao-Wen Tseng , Wai Lau
IPC分类号： H04B1/18
CPC分类号： H03J3/06 , H03F1/0277 , H03F2200/294 , H03F2200/372 , H03G1/0088 , H04B1/16
摘要： A TV tuner includes a plurality of amplifiers having inputs for coupling to an antenna, a plurality of filters having inputs coupled to outputs of the plurality of amplifiers, and a first multiplexer having inputs coupled to outputs of the plurality of filters, the first multiplexer for selecting an output of one of the filters. The TV tuner further includes a mixer having an input coupled to an output of the first multiplexer, and an output amplifier having an input coupled to an output of the mixer and an output for providing output of the TV tuner.
摘要翻译：电视调谐器包括具有用于耦合到天线的输入的多个放大器，具有耦合到多个放大器的输出的输入的多个滤波器和具有耦合到多个滤波器的输出的输入的第一多路复用器，第一多路复用器选择其中一个过滤器的输出。 TV调谐器还包括具有耦合到第一多路复用器的输出的输入的混频器，以及输出耦合到混频器的输出的输出端和用于提供TV调谐器的输出的输出。

9. 发明授权

US07548129B2 On-chip R-C time constant calibration 有权
标题翻译：片上R-C时间常数校准
公开(公告)号：US07548129B2
公开(公告)日：2009-06-16
申请号：US11552139
申请日：2006-10-23
申请人： Wai Lau , Chao-Wen Tseng , Wei-Chien Chiu , Ying-Chi Chen
发明人： Wai Lau , Chao-Wen Tseng , Wei-Chien Chiu , Ying-Chi Chen
IPC分类号： H03K3/02 , H04B1/10
CPC分类号： H03H11/1291 , H03H7/0153 , H03H2210/043 , H03K3/0231 , H03K3/02337
摘要： An integrated tuner includes circuitry to receive a television signal, a quadrature mixer coupled to the output of the circuitry, a polyphase filter coupled to the output of the quadrature mixer, a relaxation oscillator, and a digital calibration module. The relaxation oscillator generates a clock having a period that is directly proportional to the on-chip RC time constant. The clock is fed into a counter of the digital calibration module. The counter is started and stopped at predefined time intervals by a finite state machine. The finite state machine updates the calibration code based on a successive approximation algorithm according to the end count results received from the counter. The digital calibration module outputs the updated calibration code to the polyphase filter and to the relaxation oscillator.
摘要翻译：集成调谐器包括接收电视信号的电路，耦合到电路的输出的正交混频器，耦合到正交混频器的输出的多相滤波器，张弛振荡器和数字校准模块。张弛振荡器产生具有与片上RC时间常数成正比的周期的时钟。时钟被馈送到数字校准模块的计数器。计数器由有限状态机以预定义的时间间隔启动和停止。有限状态机根据从计数器接收的结束计数结果，基于逐次逼近算法来更新校准码。数字校准模块将更新的校准代码输出到多相滤波器和张弛振荡器。

10. 发明申请

US20070251896A1 Medium Disc Filing Means and Disc Storage Means Incorporating Same 审中-公开
标题翻译：具有相同的中盘装置和盘存储装置
公开(公告)号：US20070251896A1
公开(公告)日：2007-11-01
申请号：US11547665
申请日：2005-04-04
申请人： Wai Lau
发明人： Wai Lau
IPC分类号： A47G29/00
CPC分类号： G11B33/0444 , G11B33/0472
摘要： A medium disc filing means comprises a filing rail (20) and a plurality of detachable disc holders (30), the filing rail comprises a rail body and a pair of transversally protruding flanges (21,22), each disc holder comprises an attachment member and a medium disc receptacle, the attachment member comprises a clipping aperture (37) which is resiliently deformable so that the clipping aperture can be deformed to overcome the transversal width of the pair of flanges when a disc holder is to be attached to or detached from the filing rail. Such a filing means provides improved reliability and convenience since medium discs can be placed at selective locations on the filing rail and a filing order can be reasonably maintained due to clipping engagement between the filing rail and the disc holders.
摘要翻译：一种中等盘片装置包括一个盘状轨道（20）和多个可拆卸的盘片保持器（30），该导轨包括轨道体和一对横向突出的凸缘（21,22），每个盘片保持器包括一个附接构件和介质盘容器，所述附接构件包括剪切孔（37），所述剪切孔（37）可弹性变形，使得当盘保持器将被附接到或从其拆卸时，所述夹持孔可以变形以克服所述一对凸缘的横向宽度档案栏。这种归档装置提供了改进的可靠性和便利性，因为中等盘可以放置在档案轨上的选择性位置，并且由于档案轨道和盘保持器之间的夹紧接合可以合理地保持归档顺序。

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