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1. 发明授权

US07989338B2 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects 有权
标题翻译：用于CU互连中的应力迁移和电迁移改进的谷物边界阻塞
公开(公告)号：US07989338B2
公开(公告)日：2011-08-02
申请号：US11153747
申请日：2005-06-15
申请人： Fan Zhang , Kho Liep Chok , Alex See , Cheng-Cheh Tan , Xiaomei Bu , Tae Jong Lee , Liang Choo Hsia
发明人： Fan Zhang , Kho Liep Chok , Alex See , Cheng-Cheh Tan , Xiaomei Bu , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76859 , H01L21/76856 , H01L21/76864
摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
摘要翻译：用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。稍后通过平坦化处理去除阻挡层。在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

2. 发明授权

US07585768B2 Combined copper plating method to improve gap fill 有权
标题翻译：组合镀铜方法提高间隙填充
公开(公告)号：US07585768B2
公开(公告)日：2009-09-08
申请号：US11454397
申请日：2006-06-16
申请人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/2885 , H01L21/76873 , H01L21/76877
摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
摘要翻译：公开了一种在电介质层中填充间隙的方法。提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。然后使用ECP来完成间隙的铜填充。对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

3. 发明申请

US20060030128A1 Structure and method of liner air gap formation 有权
标题翻译：衬里气隙形成的结构和方法
公开(公告)号：US20060030128A1
公开(公告)日：2006-02-09
申请号：US10910499
申请日：2004-08-03
申请人： Xiaomei Bu , Alex See , Tae Lee , Fan Zhang , Yeon Lim , Liang Hsia
发明人： Xiaomei Bu , Alex See , Tae Lee , Fan Zhang , Yeon Lim , Liang Hsia
IPC分类号： H01L21/78
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.
摘要翻译：一种半导体器件的结构和方法，衬底气隙靠近互连和电介质层。介电层形成在衬底上的下介电层和下互连之上。我们在电介质层中形成互连开口。开口具有介电层的侧壁。牺牲衬垫形成在互连开口的侧壁上。形成填充开口的上互连。我们移除牺牲衬垫/垫片以形成（空气）衬垫间隙。

4. 发明授权

US07094669B2 Structure and method of liner air gap formation 有权
公开(公告)号：US07094669B2
公开(公告)日：2006-08-22
申请号：US10910499
申请日：2004-08-03
申请人： Xiaomei Bu , Alex See , Tae Jong Lee , Fan Zhang , Yeon Kheng Lim , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Tae Jong Lee , Fan Zhang , Yeon Kheng Lim , Liang Choo Hsia
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301 , H01L21/76 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

5. 发明授权

US07224060B2 Integrated circuit with protective moat 有权
标题翻译：集成电路与防护护城河
公开(公告)号：US07224060B2
公开(公告)日：2007-05-29
申请号：US10768796
申请日：2004-01-30
申请人： Fan Zhang , Kho Liep Chok , Tae Jong Lee , Xiaomei Bu , Meng Luo , Chian Yuh Sin , Yee Mei Foong , Luona Goh , Liang Choo Hsia , Huey Ming Chong
发明人： Fan Zhang , Kho Liep Chok , Tae Jong Lee , Xiaomei Bu , Meng Luo , Chian Yuh Sin , Yee Mei Foong , Luona Goh , Liang Choo Hsia , Huey Ming Chong
IPC分类号： H01L23/04
CPC分类号： H01L23/585 , H01L23/3192 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.
摘要翻译：制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。形成与金属线连接的接合焊盘。通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。

6. 发明申请

US20070293039A1 Combined copper plating method to improve gap fill 有权
标题翻译：组合镀铜方法提高间隙填充
公开(公告)号：US20070293039A1
公开(公告)日：2007-12-20
申请号：US11454397
申请日：2006-06-16
申请人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/288 , H01L21/2885 , H01L21/76873 , H01L21/76877
摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
摘要翻译：公开了一种在电介质层中填充间隙的方法。提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。然后使用ECP来完成间隙的铜填充。对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

7. 发明申请

US20060286797A1 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects 有权
标题翻译：用于CU互连中的应力迁移和电迁移改进的谷物边界阻塞
公开(公告)号：US20060286797A1
公开(公告)日：2006-12-21
申请号：US11153747
申请日：2005-06-15
申请人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
发明人： Fan Zhang , Kho Liep , Alex See , Cheng-Cheh Tou , Xiaomei Bu , Tae Lee , Liang Hsia
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76859 , H01L21/76856 , H01L21/76864
摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
摘要翻译：用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。稍后通过平坦化处理去除阻挡层。在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

8. 发明申请

US20050167824A1 Integrated circuit with protective moat 有权
标题翻译：集成电路与防护护城河
公开(公告)号：US20050167824A1
公开(公告)日：2005-08-04
申请号：US10768796
申请日：2004-01-30
申请人： Fan Zhang , Kho Chok , Tae Lee , Xiaomei Bu , Meng Luo , Chian Sin , Yee Foong , Luona Goh , Liang Hsia , Huey Chong
发明人： Fan Zhang , Kho Chok , Tae Lee , Xiaomei Bu , Meng Luo , Chian Sin , Yee Foong , Luona Goh , Liang Hsia , Huey Chong
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L23/04 , H01L23/31 , H01L23/58 , H01L27/04
CPC分类号： H01L23/585 , H01L23/3192 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.
摘要翻译：制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。形成与金属线连接的接合焊盘。通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。

9. 发明授权

US06913994B2 Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects 失效
标题翻译：形成Cu / OSG双镶嵌结构的方法，用于高性能和可靠的互连
公开(公告)号：US06913994B2
公开(公告)日：2005-07-05
申请号：US10410122
申请日：2003-04-09
申请人： Qiang Guo , Ahila Krishnamoorthy , Xiaomei Bu , Vladimir N. Bliznetsov
发明人： Qiang Guo , Ahila Krishnamoorthy , Xiaomei Bu , Vladimir N. Bliznetsov
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/302
CPC分类号： H01L21/76808
摘要： An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top corners of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.
摘要翻译：描述了形成包括有机硅酸盐玻璃（OSG）介电层的双镶嵌结构的改进方法。遵循经过第一工艺，其中在OSG层中形成通孔，并优选在SiC层上停止。在剥离含有通孔图案的光致抗蚀剂之前，去除SiC层。在通孔中形成平坦化的BARC层，以保护暴露的衬底免受沟槽形成期间的损坏。该方法提供更高的开尔文通孔和通过链收率。避免了通孔和沟槽顶角的OSG层的损坏。此外，沟槽底部的OSG层没有点蚀。在通孔和沟槽开口中实现垂直侧壁，并且保持通孔CD。蚀刻期间的OSG损耗通过在双镶嵌序列的早期阶段去除蚀刻停止层来最小化。

10. 发明授权

US08598031B2 Reliable interconnect for semiconductor device 有权
公开(公告)号：US08598031B2
公开(公告)日：2013-12-03
申请号：US12568658
申请日：2009-09-28
申请人： Fan Zhang , Xiaomei Bu , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Fan Zhang , Xiaomei Bu , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/31127 , H01L21/31144 , H01L21/3212 , H01L21/76822 , H01L21/7684 , H01L21/76885 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.

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