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1. 发明申请

US20050205522A1 Chemical agent additives in copper CMP slurry 审中-公开
标题翻译：铜CMP浆料中的化学添加剂
公开(公告)号：US20050205522A1
公开(公告)日：2005-09-22
申请号：US11130377
申请日：2005-05-16
申请人： Paul Ho , Mei Zhou , Chockalingam Ramasamy
发明人： Paul Ho , Mei Zhou , Chockalingam Ramasamy
IPC分类号： B44C1/22 , C09G1/02 , C23F1/00 , C23F3/06
CPC分类号： C09G1/02 , C23F3/06
摘要： A polishing method is achieved comprising the following steps. A layer made of material containing a metal as a main component over a substrate having recessed portions on a surface thereof so as to fill the recessed portions with the metal layer is formed. The metal is Cu, a Cu alloy, Al, or an Al alloy. The metal layer is polished by a chemical mechanical polishing method using a slurry including a polishing agent. The polishing agent contains a chemical agent and an etching agent. The chemical agent includes at least a carbonyl derivative of benzotriazole and is responsible for forming a protective film on the surface of the metal layer by reacting with the material containing a metal as a main component. The etching agent is responsible for etching the material containing a metal as a main component.
摘要翻译：实现了以下步骤的抛光方法。形成由含有金属作为主要成分的材料制成的层，该基材在其表面上具有凹陷部分的基底上，以便用金属层填充凹陷部分。金属是Cu，Cu合金，Al或Al合金。通过使用包括抛光剂的浆料的化学机械抛光方法对金属层进行抛光。抛光剂含有化学试剂和蚀刻剂。化学试剂至少包括苯并三唑的羰基衍生物，并且负责通过与含有金属作为主要成分的材料反应在金属层的表面上形成保护膜。蚀刻剂负责蚀刻含有金属作为主要成分的材料。

2. 发明申请

US20110117701A1 Fiducial Scheme Adapted for Stacked Integrated Circuits 有权
标题翻译：适应堆叠集成电路的基准方案
公开(公告)号：US20110117701A1
公开(公告)日：2011-05-19
申请号：US13004642
申请日：2011-01-11
申请人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
发明人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
IPC分类号： H01L21/50
CPC分类号： H01L23/544 , H01L21/76898 , H01L23/481 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/0401 , H01L2224/05572 , H01L2224/08145 , H01L2224/80895 , H01L2224/81121 , H01L2224/81203 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/12 , H01L2224/05552
摘要： A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
摘要翻译：公开了集成电路基板和其中使用的基板的堆叠方法。在该方法中，提供具有顶表面和底表面的集成电路基板。衬底被垂直分割成多个层，包括其中构成集成电路元件的集成电路层和与底表面相邻的缓冲层。构建从晶片的顶表面延伸到衬底到比电路层的深度更深的对准基准。通孔布置成当从基板的底表面观察时提供基准标记的图案。可以选择图案，使得当从所述晶片的所述背面观察时，其被商业陡峭/扫描仪/接触掩模对准器识别。在基板变薄之后，然后使用对准基准标记来定位在后续处理中使用的掩模。

3. 发明授权

US07898095B2 Fiducial scheme adapted for stacked integrated circuits 有权
标题翻译：基于堆叠集成电路的基准方案
公开(公告)号：US07898095B2
公开(公告)日：2011-03-01
申请号：US11385941
申请日：2006-03-20
申请人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
发明人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/76898 , H01L23/481 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/0401 , H01L2224/05572 , H01L2224/08145 , H01L2224/80895 , H01L2224/81121 , H01L2224/81203 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/12 , H01L2224/05552
摘要： A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
摘要翻译：公开了集成电路基板和其中使用的基板的堆叠方法。在该方法中，提供具有顶表面和底表面的集成电路基板。衬底被垂直分割成多个层，包括其中构成有集成电路元件的集成电路层和与底表面相邻的缓冲层。构建从晶片的顶表面延伸到衬底到比电路层的深度更深的对准基准。通孔布置成当从基板的底表面观察时提供基准标记的图案。可以选择图案，使得当从所述晶片的所述背面观察时，商业步进/扫描器/接触掩模对准器被识别。在基板变薄之后，然后使用对准基准标记来定位在后续处理中使用的掩模。

4. 发明授权

US08222121B2 Fiducial scheme adapted for stacked integrated circuits 有权
标题翻译：基于堆叠集成电路的基准方案
公开(公告)号：US08222121B2
公开(公告)日：2012-07-17
申请号：US13004642
申请日：2011-01-11
申请人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
发明人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
IPC分类号： H01L21/00
CPC分类号： H01L23/544 , H01L21/76898 , H01L23/481 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/0401 , H01L2224/05572 , H01L2224/08145 , H01L2224/80895 , H01L2224/81121 , H01L2224/81203 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/12 , H01L2224/05552
摘要： A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
摘要翻译：公开了集成电路基板和其中使用的基板的堆叠方法。在该方法中，提供具有顶表面和底表面的集成电路基板。衬底被垂直分割成多个层，包括其中构成集成电路元件的集成电路层和与底表面相邻的缓冲层。构建从晶片的顶表面延伸到衬底到比电路层的深度更深的对准基准。通孔布置成当从基板的底表面观察时提供基准标记的图案。可以选择图案，使得当从所述晶片的所述背面观察时，商业步进/扫描器/接触掩模对准器被识别。在基板变薄之后，然后使用对准基准标记来定位在后续处理中使用的掩模。

5. 发明申请

US20070216041A1 Fiducial scheme adapted for stacked integrated circuits 有权
标题翻译：基于堆叠集成电路的基准方案
公开(公告)号：US20070216041A1
公开(公告)日：2007-09-20
申请号：US11385941
申请日：2006-03-20
申请人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
发明人： Robert Patti , Sangki Hong , Chockalingam Ramasamy
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/76898 , H01L23/481 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2224/0401 , H01L2224/05572 , H01L2224/08145 , H01L2224/80895 , H01L2224/81121 , H01L2224/81203 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/12 , H01L2224/05552
摘要： A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
摘要翻译：公开了集成电路基板和其中使用的基板的堆叠方法。在该方法中，提供具有顶表面和底表面的集成电路基板。衬底被垂直分割成多个层，包括其中构成有集成电路元件的集成电路层和与底表面相邻的缓冲层。构建从晶片的顶表面延伸到衬底到比电路层的深度更深的对准基准。通孔布置成当从基板的底表面观察时提供基准标记的图案。可以选择图案，使得当从所述晶片的所述背面观察时，其被商业陡峭/扫描仪/接触掩模对准器识别。在基板变薄之后，然后使用对准基准标记来定位在后续处理中使用的掩模。

6. 发明授权

US06225221B1 Method to deposit a copper seed layer for dual damascene interconnects 有权
标题翻译：沉积双层镶嵌铜层的方法
公开(公告)号：US06225221B1
公开(公告)日：2001-05-01
申请号：US09501966
申请日：2000-02-10
申请人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta , Chockalingam Ramasamy
发明人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta , Chockalingam Ramasamy
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76874 , H01L21/76876 , H01L2221/1089
摘要： A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.
摘要翻译：已经实现了在制造集成电路器件中沉积铜种子层的新方法。铜种子层薄且保形，非常适合随后的铜化学镀。提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。图案化的电介质层形成用于计划的双镶嵌互连的通孔和沟槽。包含钽，钛或钨的阻挡层沉积在电介质层上，以对通孔和沟槽进行排列。通过CuF2蒸汽与阻挡层的反应沉积覆盖阻挡层的铜籽晶层，并且集成电路完成。

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