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1. 发明授权

US06057240A Aqueous surfactant solution method for stripping metal plasma etch deposited oxidized metal impregnated polymer residue layers from patterned metal layers 失效
标题翻译：用于从图案化金属层剥离金属等离子体蚀刻沉积的氧化金属浸渍的聚合物残余物层的水性表面活性剂溶液方法
公开(公告)号：US06057240A
公开(公告)日：2000-05-02
申请号：US55437
申请日：1998-04-06
申请人： Mei-Sheng Zhou , Jian-Hui Ye , Simon Chooi , Young-Tong Tsai
发明人： Mei-Sheng Zhou , Jian-Hui Ye , Simon Chooi , Young-Tong Tsai
IPC分类号： C11D1/04 , C11D1/68 , C11D1/70 , C11D3/30 , C11D11/00 , H01L21/02 , H01L21/311 , H01L21/3213 , H05K3/06 , H01R13/502 , C11D9/00
CPC分类号： H01L21/02071 , B82Y10/00 , B82Y30/00 , C11D11/0047 , C11D3/30 , H01L21/31138 , H01L21/32136 , H05K3/064 , C11D1/04 , H05K2203/0793 , H05K2203/095
摘要： A method for forming a patterned metal layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket metal layer. There is then formed over the blanket metal layer a patterned photoresist layer. There is then etched through use of a plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the blanket metal layer to form a patterned metal layer. The patterned metal layer so formed has a metal impregnated carbonaceous polymer residue layer formed upon a sidewall of the patterned metal layer. There is then stripped from the patterned metal layer the patterned photoresist layer through use of an oxygen containing plasma while simultaneously oxidizing the metal impregnated carbonaceous polymer residue layer to form an oxidized metal impregnated polymer residue layer upon the sidewall of the patterned metal layer. There is then stripped from the sidewall of the patterned metal layer the oxidized metal impregnated polymer residue layer while employing an aqueous alkyl ammonium hydroxide based solution. The aqueous alkyl ammonium hydroxide based solution has incorporated therein a surfactant capable of forming a monolayer adsorbed upon the sidewall of the patterned metal layer.
摘要翻译：一种用于在微电子制造中形成图案化金属层的方法。首先提供了在微电子制造中使用的衬底。然后在衬底上形成覆盖金属层。然后在覆盖金属层上形成图案化的光致抗蚀剂层。然后通过使用等离子体蚀刻方法蚀刻，同时使用图案化的光致抗蚀剂层作为光刻胶蚀刻掩模层，覆盖金属层以形成图案化的金属层。如此形成的图案化金属层具有形成在图案化金属层的侧壁上的金属浸渍碳质聚合物残余层。然后通过使用含氧等离子体从图案化的金属层剥离图案化的光刻胶层，同时对金属浸渍的碳质聚合物残余层进行氧化，以在图案化金属层的侧壁上形成氧化金属浸渍的聚合物残余物层。然后从图案化金属层的侧壁剥离氧化金属浸渍的聚合物残余物层，同时使用基于烷基氢氧化铵的水溶液。基于烷基氢氧化铵的水溶液溶液中加入了能够形成单层吸附在图案化金属层的侧壁上的表面活性剂。

2. 发明授权

US06987321B2 Copper diffusion deterrent interface 失效
标题翻译：铜扩散阻止界面
公开(公告)号：US06987321B2
公开(公告)日：2006-01-17
申请号：US10718865
申请日：2003-11-21
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subbash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subbash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L23/48
CPC分类号： H01L21/76844 , H01L21/28556 , H01L21/31111 , H01L21/314 , H01L21/76807
摘要： Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
摘要翻译：用于形成双镶嵌互连结构的方法和产品，其中将铜硫化物界面层作为开口的侧壁沉积阻止铜离子迁移或扩散到电介质材料中。

3. 发明授权

US06705512B2 Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding 有权
标题翻译：导电盖层在倒装芯片，芯棒和微金属接合中的应用方法
公开(公告)号：US06705512B2
公开(公告)日：2004-03-16
申请号：US10099283
申请日：2002-03-15
申请人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： B23K3102
CPC分类号： H01L24/85 , B23K20/007 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/85 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/78 , H01L2924/00
摘要： A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
摘要翻译：将接合元件接合到金属接合焊盘的方法包括以下步骤。提供了一种在层开口内具有暴露的凹陷金属接合焊盘的半导体结构。该层具有上表面。在金属焊盘上形成具有预定厚度的导电盖。接合元件结合到导电盖以与金属接合焊盘形成电连接。

4. 发明授权

US06565664B2 Method for stripping copper in damascene interconnects 有权
公开(公告)号：US06565664B2
公开(公告)日：2003-05-20
申请号：US10131519
申请日：2002-04-24
申请人： Subhash Gupta , Simon Chooi , Paul Ho , Mei Sheng Zhou
发明人： Subhash Gupta , Simon Chooi , Paul Ho , Mei Sheng Zhou
IPC分类号： C23G114
CPC分类号： H01L21/32134 , C23F1/34 , H01L21/7684 , Y10S134/902
摘要： An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

5. 发明授权

US06524910B1 Method of forming dual thickness gate dielectric structures via use of silicon nitride layers 失效
标题翻译：通过使用氮化硅层形成双厚度栅极电介质结构的方法
公开(公告)号：US06524910B1
公开(公告)日：2003-02-25
申请号：US09670329
申请日：2000-09-27
申请人： Wenhe Lin , Kin Leong Pey , Mei Sheng Zhou , Zhong Dong , Simon Chooi
发明人： Wenhe Lin , Kin Leong Pey , Mei Sheng Zhou , Zhong Dong , Simon Chooi
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/02238 , H01L21/02255 , H01L21/02304 , H01L21/28194 , H01L21/31662 , H01L21/823462 , H01L29/513 , H01L29/518
摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.
摘要翻译：已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层对于较高电压门结构。第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。

6. 发明授权

US06479383B1 Method for selective removal of unreacted metal after silicidation 有权
标题翻译：硅化后选择性去除未反应金属的方法
公开(公告)号：US06479383B1
公开(公告)日：2002-11-12
申请号：US10068823
申请日：2002-02-05
申请人： Simon Chooi , Mei Sheng Zhou
发明人： Simon Chooi , Mei Sheng Zhou
IPC分类号： H01L2144
CPC分类号： H01L21/32134 , H01L21/28518 , H01L21/321
摘要： A method to remove a metal from over a substrate in the fabrication of an integrated circuit device. The invention comprises providing a metal layer over a substrate. The metal layer is exposed to a reactant gas to form at least a solid metal containing product. The reactant gas preferably contains sulfur and oxygen. The reactant gas more preferably comprises sulfur dioxide or sulfur trioxide. The reactant gas is preferably heated and optionally exposed to a plasma. Next, the metal containing product is removed using a liquid, thereby removing at least portion of the metal layer from over the substrate.
摘要翻译：一种在制造集成电路器件中从衬底上去除金属的方法。本发明包括在衬底上提供金属层。金属层暴露于反应气体中以形成至少含固体金属的产品。反应气体优选含有硫和氧。反应气体更优选包含二氧化硫或三氧化硫。反应气体优选被加热并任选地暴露于等离子体。接下来，使用液体除去含金属的产品，从而从基板上除去金属层的至少一部分。

7. 发明授权

US06429129B1 Method of using silicon rich carbide as a barrier material for fluorinated materials 失效
公开(公告)号：US06429129B1
公开(公告)日：2002-08-06
申请号：US09594415
申请日：2000-06-16
申请人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
发明人： Licheng Han , Xu Yi , Simon Chooi , Mei Sheng Zhou , Joseph Zhifeng Xie
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/3127 , H01L21/314 , H01L21/31629 , H01L21/76801 , H01L21/76807 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

8. 发明授权

US06415973B1 Method of application of copper solution in flip-chip, COB, and micrometal bonding 失效
标题翻译：铜溶液在倒装芯片，COB和微结合中的应用方法
公开(公告)号：US06415973B1
公开(公告)日：2002-07-09
申请号：US09618672
申请日：2000-07-18
申请人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Mei Sheng Zhou , Yakub Aliyu , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Mei Sheng Zhou , Yakub Aliyu , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： B23K106
CPC分类号： H01L24/85 , B23K1/19 , B23K2101/40 , B23K2103/12 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48647 , H01L2224/48747 , H01L2224/48847 , H01L2224/48992 , H01L2224/8592 , H01L2224/85948 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/78 , H01L2924/00
摘要： A method of bonding a bonding element to a metal bonding pad, comprising the following steps. A semiconductor structure having an exposed metal bonding pad within a passivation layer opening is provided. The bonding pad has an upper surface. A bonding element is positioned to contact the bonding pad upper surface. A bonding solution is applied within the passivation layer opening, covering the bonding pad and a portion of the bonding element. The structure is annealed by heating said bonding element to selectively solidify the bonding solution proximate said contact of said bonding element to said bonding pad, bonding the bonding element to the bonding pad.
摘要翻译：一种将接合元件接合到金属接合焊盘的方法，包括以下步骤。提供了在钝化层开口内具有暴露的金属焊盘的半导体结构。接合垫具有上表面。定位接合元件以接合焊盘上表面。在钝化层开口内施加粘合溶液，覆盖粘结垫和粘合元件的一部分。通过加热所述结合元件来对所述结构进行退火，以选择性地将所述接合元件的所述接触附近的接合溶液固化到所述接合焊盘，将所述接合元件接合到所述接合焊盘。

9. 发明授权

US06358842B1 Method to form damascene interconnects with sidewall passivation to protect organic dielectrics 有权
标题翻译：形成具有侧壁钝化的镶嵌互连以保护有机电介质的方法
公开(公告)号：US06358842B1
公开(公告)日：2002-03-19
申请号：US09633770
申请日：2000-08-07
申请人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
发明人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
IPC分类号： H01L213205
CPC分类号： H01L21/76831 , H01L21/31138 , H01L21/76808
摘要： A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.
摘要翻译：已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。镶嵌互连可以是单镶嵌或双镶嵌。提供铜导体覆盖在半导体衬底上。第一钝化层被提供在铜导体上。沉积在第一钝化层上的低介电常数层。沉积覆盖在低介电常数层上的可选的覆盖层。沉积在覆盖层上的光致抗蚀剂层。覆盖层和低介电常数层被蚀刻通过以形成通孔。同时剥离光致抗蚀剂层，同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。从而防止侧壁弯曲和通过中毒。蚀刻第一钝化层以暴露下面的铜导体。沉积覆盖覆盖层并填充通孔的铜层。铜层被抛光以在集成电路器件的制造中完成镶嵌互连。

10. 发明授权

US06350675B1 Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects 失效
标题翻译：将富硅材料集成在双镶嵌互连的自对准通孔中
公开(公告)号：US06350675B1
公开(公告)日：2002-02-26
申请号：US09686282
申请日：2000-10-12
申请人： Simon Chooi , Mei-Sheng Zhou , Subhash Gupta , Yi Xu
发明人： Simon Chooi , Mei-Sheng Zhou , Subhash Gupta , Yi Xu
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L21/7681 , H01L21/76825 , H01L21/76826
摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.
摘要翻译：本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及形成自对准的双镶嵌互连和通孔，其结合了低介电常数金属间电介质（IMD）并利用甲硅烷基化的顶表面成像（TSI ）光致抗蚀剂，具有单步或多步选择性反应离子蚀刻（RIE）工艺，以形成沟槽/通孔。本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像（TSI）抗蚀剂蚀刻阻挡层以形成通孔图案。在本发明的第一和第二实施例中描述了使用顶表面成像（TSI）抗蚀剂的两种变型，其具有和不具有将暴露区域保持在适当位置，此外，使用刚好低于抗蚀剂层。提供顶表面成像（TSI）光致抗蚀剂和低介电常数金属间电介质（IMD）之间的粘附性是好的，可以省略上述薄介电层，产生本发明的第三和第四实施例。该方法中特别注意保护低介电常数金属间电介质（ILD）材料的完整性，该材料选自有机基或掺碳二氧化硅。

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