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1. 发明授权

US06987321B2 Copper diffusion deterrent interface 失效
标题翻译：铜扩散阻止界面
公开(公告)号：US06987321B2
公开(公告)日：2006-01-17
申请号：US10718865
申请日：2003-11-21
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subbash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subbash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L23/48
CPC分类号： H01L21/76844 , H01L21/28556 , H01L21/31111 , H01L21/314 , H01L21/76807
摘要： Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
摘要翻译：用于形成双镶嵌互连结构的方法和产品，其中将铜硫化物界面层作为开口的侧壁沉积阻止铜离子迁移或扩散到电介质材料中。

2. 发明授权

US06705512B2 Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding 有权
标题翻译：导电盖层在倒装芯片，芯棒和微金属接合中的应用方法
公开(公告)号：US06705512B2
公开(公告)日：2004-03-16
申请号：US10099283
申请日：2002-03-15
申请人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： B23K3102
CPC分类号： H01L24/85 , B23K20/007 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/85 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/78 , H01L2924/00
摘要： A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
摘要翻译：将接合元件接合到金属接合焊盘的方法包括以下步骤。提供了一种在层开口内具有暴露的凹陷金属接合焊盘的半导体结构。该层具有上表面。在金属焊盘上形成具有预定厚度的导电盖。接合元件结合到导电盖以与金属接合焊盘形成电连接。

3. 发明授权

US06415973B1 Method of application of copper solution in flip-chip, COB, and micrometal bonding 失效
标题翻译：铜溶液在倒装芯片，COB和微结合中的应用方法
公开(公告)号：US06415973B1
公开(公告)日：2002-07-09
申请号：US09618672
申请日：2000-07-18
申请人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Mei Sheng Zhou , Yakub Aliyu , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
发明人： Kwok Keung Paul Ho , Simon Chooi , Yi Xu , Mei Sheng Zhou , Yakub Aliyu , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy
IPC分类号： B23K106
CPC分类号： H01L24/85 , B23K1/19 , B23K2101/40 , B23K2103/12 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48647 , H01L2224/48747 , H01L2224/48847 , H01L2224/48992 , H01L2224/8592 , H01L2224/85948 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/78 , H01L2924/00
摘要： A method of bonding a bonding element to a metal bonding pad, comprising the following steps. A semiconductor structure having an exposed metal bonding pad within a passivation layer opening is provided. The bonding pad has an upper surface. A bonding element is positioned to contact the bonding pad upper surface. A bonding solution is applied within the passivation layer opening, covering the bonding pad and a portion of the bonding element. The structure is annealed by heating said bonding element to selectively solidify the bonding solution proximate said contact of said bonding element to said bonding pad, bonding the bonding element to the bonding pad.
摘要翻译：一种将接合元件接合到金属接合焊盘的方法，包括以下步骤。提供了在钝化层开口内具有暴露的金属焊盘的半导体结构。接合垫具有上表面。定位接合元件以接合焊盘上表面。在钝化层开口内施加粘合溶液，覆盖粘结垫和粘合元件的一部分。通过加热所述结合元件来对所述结构进行退火，以选择性地将所述接合元件的所述接触附近的接合溶液固化到所述接合焊盘，将所述接合元件接合到所述接合焊盘。

4. 发明授权

US06358842B1 Method to form damascene interconnects with sidewall passivation to protect organic dielectrics 有权
标题翻译：形成具有侧壁钝化的镶嵌互连以保护有机电介质的方法
公开(公告)号：US06358842B1
公开(公告)日：2002-03-19
申请号：US09633770
申请日：2000-08-07
申请人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
发明人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
IPC分类号： H01L213205
CPC分类号： H01L21/76831 , H01L21/31138 , H01L21/76808
摘要： A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.
摘要翻译：已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。镶嵌互连可以是单镶嵌或双镶嵌。提供铜导体覆盖在半导体衬底上。第一钝化层被提供在铜导体上。沉积在第一钝化层上的低介电常数层。沉积覆盖在低介电常数层上的可选的覆盖层。沉积在覆盖层上的光致抗蚀剂层。覆盖层和低介电常数层被蚀刻通过以形成通孔。同时剥离光致抗蚀剂层，同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。从而防止侧壁弯曲和通过中毒。蚀刻第一钝化层以暴露下面的铜导体。沉积覆盖覆盖层并填充通孔的铜层。铜层被抛光以在集成电路器件的制造中完成镶嵌互连。

5. 发明授权

US06350675B1 Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects 失效
标题翻译：将富硅材料集成在双镶嵌互连的自对准通孔中
公开(公告)号：US06350675B1
公开(公告)日：2002-02-26
申请号：US09686282
申请日：2000-10-12
申请人： Simon Chooi , Mei-Sheng Zhou , Subhash Gupta , Yi Xu
发明人： Simon Chooi , Mei-Sheng Zhou , Subhash Gupta , Yi Xu
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L21/7681 , H01L21/76825 , H01L21/76826
摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.
摘要翻译：本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及形成自对准的双镶嵌互连和通孔，其结合了低介电常数金属间电介质（IMD）并利用甲硅烷基化的顶表面成像（TSI ）光致抗蚀剂，具有单步或多步选择性反应离子蚀刻（RIE）工艺，以形成沟槽/通孔。本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像（TSI）抗蚀剂蚀刻阻挡层以形成通孔图案。在本发明的第一和第二实施例中描述了使用顶表面成像（TSI）抗蚀剂的两种变型，其具有和不具有将暴露区域保持在适当位置，此外，使用刚好低于抗蚀剂层。提供顶表面成像（TSI）光致抗蚀剂和低介电常数金属间电介质（IMD）之间的粘附性是好的，可以省略上述薄介电层，产生本发明的第三和第四实施例。该方法中特别注意保护低介电常数金属间电介质（ILD）材料的完整性，该材料选自有机基或掺碳二氧化硅。

6. 发明授权

US06165891A Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer 有权
标题翻译：使用碳氮化物，氮化硼或氮化硼钝化层，蚀刻停止层和/或覆盖层的具有降低的电容的镶嵌结构
公开(公告)号：US06165891A
公开(公告)日：2000-12-26
申请号：US435434
申请日：1999-11-22
申请人： Simon Chooi , Yi Xu , Mei Sheng Zhou
发明人： Simon Chooi , Yi Xu , Mei Sheng Zhou
IPC分类号： H01L21/311 , H01L21/318 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763 , G03C5/00 , H01L21/302 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/31122 , H01L21/318 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.
摘要翻译：通过使用包含碳氮化物，氮化硼或碳氮化硼的低介电常数材料通过形成钝化层，蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。该方法开始于提供其上具有第一导电层的半导体结构。在第一导电层上形成钝化层。第一电介质层形成在钝化层之上，并且在第一介电层上形成蚀刻停止层。第二介电层形成在蚀刻停止层上方，并且可以在第二介电层上形成任选的盖层。图案化盖层，第二电介质层，蚀刻停止层和第一介电层，以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。碳氮化物钝化层，蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。可以通过使用B2H6，氨和氮的PECVD形成氮化硼钝化层，蚀刻停止层或盖层。硼氮化物钝化层，蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。

7. 发明授权

US07452808B2 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 失效
标题翻译：使用导电聚合物铜/铜表面键合方法应用于IC芯片接合
公开(公告)号：US07452808B2
公开(公告)日：2008-11-18
申请号：US10988768
申请日：2004-11-15
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
IPC分类号： H01L21/44
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
摘要翻译：提供了具有暴露的金属端接垫的半导体芯片，以及在其上具有对应的暴露的金属凸块的单独的基板。在暴露的金属端接垫上形成导电聚合物塞。在导电聚合物塞上形成一个符合标准的界面层。半导体芯片的导电聚合物插塞与相应的金属凸块对准。导电聚合物塞上的一致界面层与相应的金属凸块配合。一致的界面层被热分解，粘附和永久地附着导电聚合物塞与相应的金属凸块。还公开了形成和图案化羰基镍层的方法。

8. 发明授权

US06967162B2 Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding 有权
公开(公告)号：US06967162B2
公开(公告)日：2005-11-22
申请号：US10988769
申请日：2004-11-15
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Sudijono , Subhash Gupta , Sudipto Roy , Paul Ho , Yi Xu
IPC分类号： H01L21/44 , H01L21/50 , H01L21/60 , H01L23/48 , H01L23/485 , H01L23/52 , H01L29/40
CPC分类号： H01L24/13 , H01L24/11 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13147 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

9. 发明授权

US06436824B1 Low dielectric constant materials for copper damascene 有权
标题翻译：用于铜镶嵌的低介电常数材料
公开(公告)号：US06436824B1
公开(公告)日：2002-08-20
申请号：US09346526
申请日：1999-07-02
申请人： Simon Chooi , Mei Sheng Zhou , Yi Xu
发明人： Simon Chooi , Mei Sheng Zhou , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L21/02211 , H01L21/02167 , H01L21/02274 , H01L21/3125 , H01L21/314 , H01L21/76807
摘要： Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.
摘要翻译：提供了用于双镶嵌工艺中的电介质的新型低介电常数材料。通过在等离子体增强化学沉积室中使含氮前体和取代的有机硅烷反应形成低介电常数材料介电层。此外，提供了用于双镶嵌工艺中的钝化或蚀刻停止层的新型低介电常数材料。通过在等离子体增强化学沉积室中使取代的氨前体和取代的有机硅烷反应形成具有低介电约束的碳掺杂的氮化硅钝化或蚀刻停止层。或者，通过在等离子体增强化学沉积室中使取代的有机硅烷反应形成具有低介电常数的碳化硅钝化或蚀刻停止层。此外，描述了形成用于双镶嵌工艺中的钝化，电介质和蚀刻停止层的集成工艺。

10. 发明授权

US06683002B1 Method to create a copper diffusion deterrent interface 失效
公开(公告)号：US06683002B1
公开(公告)日：2004-01-27
申请号：US09636580
申请日：2000-08-10
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subhash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/28556 , H01L21/31111 , H01L21/314 , H01L21/76807
摘要： Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

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