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1. 发明授权

US5781474A Parallel programming method of memory words and corresponding circuit 失效
标题翻译：存储字和相应电路的并行编程方法
公开(公告)号：US5781474A
公开(公告)日：1998-07-14
申请号：US722378
申请日：1996-09-30
申请人： Mauro Sali , Fabio Tassan Caser , Stefan Schippers
发明人： Mauro Sali , Fabio Tassan Caser , Stefan Schippers
IPC分类号： G11C17/00 , G11C16/06 , G11C16/10 , G11C16/24 , G11C29/34 , G11C11/34
CPC分类号： G11C16/24 , G11C16/10 , G11C29/34
摘要： A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of floating gate memory cells with corresponding drain terminals heading columns or bit lines of the matrix and supplied during the programming stage with a drain voltage which is boosted with respect to a supply voltage (Vcc). During the parallel programming stage the supply voltage is used as a drain voltage. Switching is provided between the supply using the drain voltage or the supply voltage during the transient between single word programming and parallel programming.
摘要翻译：一种用于在电可编程非易失性半导体存储器件中并行编程存储器字的方法，包括至少一个浮动栅极存储器单元矩阵，其具有相应的漏极端子标题列或矩阵的位线，并在编程阶段期间以漏极电压其相对于电源电压（Vcc）被提升。在并行编程阶段，电源电压用作漏极电压。在单字编程和并行编程之间的瞬态期间，使用漏极电压或电源电压之间提供切换。

2. 发明授权

US5848013A Row decoding circuit for semiconductor non-volatile electrically programmable memory and corresponding method 失效
标题翻译：半导体非易失性电可编程存储器的行解码电路及相应的方法
公开(公告)号：US5848013A
公开(公告)日：1998-12-08
申请号：US824616
申请日：1997-03-27
申请人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
发明人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
IPC分类号： G11C8/10 , G11C16/08 , G11C8/00
CPC分类号： G11C8/10 , G11C16/08
摘要： The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
摘要翻译：本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。耗尽晶体管的控制端构成电路的另一输入。

3. 发明授权

US06320792B1 Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method 有权
标题翻译：半导体非易失性电可编程存储器的行解码电路及相应的方法
公开(公告)号：US06320792B1
公开(公告)日：2001-11-20
申请号：US09633334
申请日：2000-08-07
申请人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
发明人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
IPC分类号： G11C1606
CPC分类号： G11C8/10 , G11C16/08
摘要： The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
摘要翻译：本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。耗尽晶体管的控制端构成电路的另一输入。

4. 发明授权

US6137725A Row decoding circuit for a semiconductor non-volatile electrically programmable memory and corresponding method 有权
标题翻译：半导体非易失性电可编程存储器的行解码电路及相应的方法
公开(公告)号：US6137725A
公开(公告)日：2000-10-24
申请号：US203937
申请日：1998-12-02
申请人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
发明人： Fabio Tassan Caser , Mauro Sali , Marcello Cane
IPC分类号： G11C8/10 , G11C16/08 , G11C16/06
CPC分类号： G11C8/10 , G11C16/08
摘要： The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
摘要翻译：本发明涉及一种用于电可编程和可擦除的半导体非易失性存储装置的行解码电路，该电路可编程和可擦除半导体非易失性存储装置包括布置为单元行和列的存储单元的矩阵，并被划分为扇区，所述电路是输入行解码信号和电源电压，以分别驱动并入一对互补的上拉和下拉型高压MOS晶体管的输出级，所述高压MOS晶体管被连接以形成连接到所述上拉和下拉的一个扇区的行的输出端子矩阵，其特征在于，在输出端和下拉晶体管之间提供具有增强的栅极氧化物的P沟道耗尽型的MOS晶体管。耗尽晶体管的控制端构成电路的另一输入。

5. 发明授权

US5844404A Voltage regulator for semiconductor non-volatile electrically programmable memory device 失效
标题翻译：用于半导体非易失性电可编程存储器件的稳压器
公开(公告)号：US5844404A
公开(公告)日：1998-12-01
申请号：US720491
申请日：1996-09-30
申请人： Fabio Tassan Caser , Stefan Schippers , Marcello Cane
发明人： Fabio Tassan Caser , Stefan Schippers , Marcello Cane
IPC分类号： G11C5/14 , G11C16/30 , G05F3/24
CPC分类号： G11C16/30 , G11C5/147
摘要： A voltage regulator for electrically programmable non-volatile memory cells includes a gain stage which is supplied a voltage from a voltage booster connected to a supply voltage reference, having an input terminal connected to an output of a voltage divider and an output terminal connected to a pull-up transistor of a pull-up and pull-down differential pair to output the regulated voltage for programming at least one column or bit line of the memory cells. The voltage regulator also includes a second gain stage having an input terminal connected to a second output of the voltage divider. The second stage has an output connected to turn on the pull-down transistor in the complementary pair upon the regulated voltage exceeding a predetermined value.
摘要翻译：用于电可编程非易失性存储单元的电压调节器包括增益级，其从连接到电源电压基准的升压器提供电压，其具有连接到分压器的输出的输入端子和连接到上拉和下拉差分对的上拉晶体管输出调节电压，用于对存储单元的至少一列或位线进行编程。电压调节器还包括具有连接到分压器的第二输出的输入端的第二增益级。第二级具有连接的输出端，以便在调节电压超过预定值时，互补对中的下拉晶体管导通。

6. 发明申请

US20080165585A1 ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES 有权
标题翻译：用于NAND型闪存存储器的擦除验证方法
公开(公告)号：US20080165585A1
公开(公告)日：2008-07-10
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

7. 发明申请

US20080136500A1 CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS 有权
标题翻译：用于产生多个输出电压的充电泵
公开(公告)号：US20080136500A1
公开(公告)日：2008-06-12
申请号：US11608941
申请日：2006-12-11
申请人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
发明人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

8. 发明授权

US07333389B2 Column decoding architecture for flash memories 有权
标题翻译：闪存的列解码架构
公开(公告)号：US07333389B2
公开(公告)日：2008-02-19
申请号：US11126441
申请日：2005-05-11
申请人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
发明人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/26
摘要： An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
摘要翻译：用于闪存器件的列解码的改进方法和装置利用长度大于逻辑页长度的突发页。当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。只有当读取跨越突发页面边界时，存储器件才进入等待状态。这使存储器件进入等待状态的时间量最小化。在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。不需要对架构或列解码器选择器的数量进行更改。因此，同步读取期间的存储器访问时间得到改善。

9. 发明授权

US07130209B2 Flexible OTP sector protection architecture for flash memories 有权
标题翻译：灵活的OTP扇区保护架构，用于闪存
公开(公告)号：US07130209B2
公开(公告)日：2006-10-31
申请号：US11128648
申请日：2005-05-12
申请人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
发明人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块的存储器不被修改的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止修改块的部分。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

10. 发明申请

US20060077714A1 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US20060077714A1
公开(公告)日：2006-04-13
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

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