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1. 发明授权

US07723235B2 Method for smoothing a resist pattern prior to etching a layer using the resist pattern 失效
标题翻译：在使用抗蚀剂图案蚀刻层之前使抗蚀剂图案平坦化的方法
公开(公告)号：US07723235B2
公开(公告)日：2010-05-25
申请号：US11571853
申请日：2005-06-10
申请人： Masaru Kurihara , Masaru Izawa
发明人： Masaru Kurihara , Masaru Izawa
IPC分类号： H01L21/311 , H01L21/3065
CPC分类号： H01L21/28035 , H01L21/0273 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L21/76802 , H01L21/76885 , H01L29/6659 , H01L29/7833
摘要： After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21) (step S3). Then, a passivation film (23) is deposited on the antireflection film (21) so as to cover the resist pattern (22) by plasma using fluorocarbon gas while a bias voltage is being applied to the semiconductor substrate (step S4). Then, the passivation film (23) and the antireflection film (21) are etched by plasma using gas containing oxygen gas (step S5). Thereafter, the polycrystalline silicon film (5) is etched using the resist pattern (22) with reduced line edge roughness as an etching mask to form a gate electrode (step S6).
摘要翻译：在通过栅极绝缘膜用绝缘膜在半导体基板上形成多晶硅膜（5）（步骤S1）之后，在多晶硅膜（5）上形成有机防反射膜（21）（步骤S2）并且在防反射膜（21）上形成抗蚀剂图案（22）（步骤S3）。然后，在防反射膜（21）上沉积钝化膜（23），以便在对半导体衬底施加偏置电压的同时使用碳氟化合物气体通过等离子体覆盖抗蚀剂图案（步骤S4）。然后，使用含氧气体的等离子体蚀刻钝化膜（23）和防反射膜（21）（步骤S5）。此后，使用具有减小的线边缘粗糙度的抗蚀剂图案（22）蚀刻多晶硅膜（5）作为蚀刻掩模以形成栅电极（步骤S6）。

2. 发明申请

US20080319709A1 DIMENSION MEASURING APPARATUS AND DIMENSION MEASURING METHOD FOR SEMICONDUCTOR DEVICE 有权
标题翻译：尺寸测量装置和半导体器件的尺寸测量方法
公开(公告)号：US20080319709A1
公开(公告)日：2008-12-25
申请号：US12128364
申请日：2008-05-28
申请人： Masaru KURIHARA , Masaru Izawa , Junichi Tanaka
发明人： Masaru KURIHARA , Masaru Izawa , Junichi Tanaka
IPC分类号： G01B21/00
CPC分类号： H01L22/12 , H01J2237/2813
摘要： A dimension of a specific part of a semiconductor device is measured with high accuracy and at a high speed.The invention provides a dimension measuring apparatus used for measuring a dimension of a semiconductor device having a first pattern of repeated structure and a second pattern that is linear and formed on the first pattern to extend over the repeated structure. The dimension measuring apparatus comprises: a shape information acquisition means, which acquires information on a shape of the first pattern; a width value acquisition means, which acquires a width value of each portion of the second pattern on a basis of an observation result of the second pattern by a microscope; an analytic area setting means, which sets a plurality of analytic areas on the second pattern such that the analytic areas are adapted for the first pattern's shape acquired by the shape information acquisition means; and a dimension determining means, which extracts, for each of the set analytic areas, width values of portions included in the analytic area in question out of width values acquired by the width value acquisition means, and uses the extracted width values to determine a dimension of the second pattern at portions overlapping the first pattern.
摘要翻译：半导体器件的特定部分的尺寸以高精度和高速度被测量。本发明提供了一种用于测量具有重复结构的第一图案的半导体器件的尺寸的尺寸测量装置，以及线性形成在第一图案上以在重复结构上延伸的第二图案。尺寸测量装置包括：形状信息获取装置，其获取关于第一图案的形状的信息; 宽度值获取装置，其基于通过显微镜的第二图案的观察结果获取第二图案的每个部分的宽度值; 分析区域设置装置，其在第二图案上设置多个分析区域，使得分析区域适于由形状信息获取装置获取的第一图案的形状; 以及维度确定装置，其针对每个所设定的分析区域提取由所述宽度值获取装置获取的宽度值中包含在所述分析区域中的部分的宽度值，并且使用所提取的宽度值来确定尺寸在与第一图案重叠的部分处的第二图案。

3. 发明授权

US07915055B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07915055B2
公开(公告)日：2011-03-29
申请号：US11693776
申请日：2007-03-30
申请人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
发明人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a manufacturing technique of a semiconductor device that reduces fluctuation of electric characteristic and a working size of a semiconductor device and can manufacture semiconductor devices at high quality and at high yield. In a semiconductor device manufacturing system, a control method for a manufacturing process of a semiconductor device having a function (a data collecting unit) of collecting examination data at a plurality of examining steps including an examining step of setting a length of a measurement region in a wiring direction to at least 10 times a wire width to measure the wire width and an examining step of examining the wire width, a function (a data analyzing unit) of generating a prediction model of electric characteristic or working size of a semiconductor device using the examination data to generate a control model from the prediction model, and a function (a process control unit) of properly controlling processing conditions for a control process based upon examination data of the plurality of examining steps in the manufacturing process of a semiconductor device and the control model is realized.
摘要翻译：本发明提供一种能够降低半导体装置的电气特性和工作尺寸的波动的半导体装置的制造技术，能够高质量，高产率地制造半导体装置。在半导体器件制造系统中，具有在多个检查步骤中收集检查数据的功能（数据收集单元）的半导体器件的制造过程的控制方法包括将测量区域的长度设置在布线方向为线宽的至少10倍以测量线宽度和检查线宽度的检查步骤，产生半导体器件的电特性或工作尺寸的预测模型的功能（数据分析单元），其使用根据预测模型生成控制模型的检查数据和根据半导体装置的制造过程中的多个检查步骤的检查数据适当地控制用于控制处理的处理条件的功能（过程控制单元），以及实现了控制模型。

4. 发明授权

US07720632B2 Dimension measuring apparatus and dimension measuring method for semiconductor device 有权
标题翻译：半导体器件的尺寸测量装置和尺寸测量方法
公开(公告)号：US07720632B2
公开(公告)日：2010-05-18
申请号：US12128364
申请日：2008-05-28
申请人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
发明人： Masaru Kurihara , Masaru Izawa , Junichi Tanaka
IPC分类号： G01B15/00 , G01N23/00
CPC分类号： H01L22/12 , H01J2237/2813
摘要： A dimension measuring apparatus used for measuring a dimension of a semiconductor device having a first pattern of repeated structure and a second pattern that is linear and formed on the first pattern to extend over the repeated structure. The invention includes a shape information acquisition unit which acquires information on a shape of the first pattern; a width value acquisition unit which acquires a width value of each portion of the second pattern; an analytic area setting unit, which sets a plurality of analytic areas on the second pattern; and a dimension determining unit, which extracts, for each of the set analytic areas, width values of portions included in the analytic area, and uses the extracted width values to determine a dimension of the second pattern at portions overlapping the first pattern.
摘要翻译：一种尺寸测量装置，用于测量具有重复结构的第一图案和第二图案的半导体器件的尺寸，该第二图案是线性的并形成在第一图案上以在重复结构上延伸。本发明包括获取关于第一图案的形状的信息的形状信息获取单元; 宽度值获取单元，其获取所述第二图案的每个部分的宽度值; 分析区域设置单元，其设置所述第二图案上的多个分析区域; 以及尺寸确定单元，其针对每个所述分析区域提取包括在所述分析区域中的部分的宽度值，并且使用所提取的宽度值来确定与所述第一图案重叠的部分处的所述第二图案的尺寸。

5. 发明申请

US20080045022A1 Semiconductor Device Manufacturing Method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20080045022A1
公开(公告)日：2008-02-21
申请号：US11571853
申请日：2005-06-10
申请人： Masaru Kurihara , Masaru Izawa
发明人： Masaru Kurihara , Masaru Izawa
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L29/423 , H01L29/78
CPC分类号： H01L21/28035 , H01L21/0273 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L21/76802 , H01L21/76885 , H01L29/6659 , H01L29/7833
摘要： After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21) (step S3). Then, a passivation film (23) is deposited on the antireflection film (21) so as to cover the resist pattern (22) by plasma using fluorocarbon gas while a bias voltage is being applied to the semiconductor substrate (step S4). Then, the passivation film (23) and the antireflection film (21) are etched by plasma using gas containing oxygen gas (step S5). Thereafter, the polycrystalline silicon film (5) is etched using the resist pattern (22) with reduced line edge roughness as an etching mask to form a gate electrode (step S6).
摘要翻译：在通过栅极绝缘膜用绝缘膜在半导体基板上形成多晶硅膜（5）（步骤S1）后，在多晶硅膜（5）上形成有机抗反射膜（步骤S2）），并且在防反射膜（21）上形成抗蚀剂图案（22）（步骤S3）。然后，在防反射膜（21）上沉积钝化膜（23），以便在对半导体衬底施加偏置电压的同时使用碳氟化合物气体通过等离子体覆盖抗蚀剂图案（步骤S4）。然后，使用含氧气体的等离子体蚀刻钝化膜（23）和抗反射膜（步骤S5）。此后，使用具有减小的线边缘粗糙度的抗蚀剂图案（22）蚀刻多晶硅膜（5）作为蚀刻掩模以形成栅电极（步骤S6）。

6. 发明申请

US20070238204A1 Manufacturing Method of Semiconductor Device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20070238204A1
公开(公告)日：2007-10-11
申请号：US11693776
申请日：2007-03-30
申请人： MASARU KURIHARA , Masaru Izawa , Junichi Tanaka
发明人： MASARU KURIHARA , Masaru Izawa , Junichi Tanaka
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a manufacturing technique of a semiconductor device that reduces fluctuation of electric characteristic and a working size of a semiconductor device and can manufacture semiconductor devices at high quality and at high yield. In a semiconductor device manufacturing system, a control method for a manufacturing process of a semiconductor device having a function (a data collecting unit) of collecting examination data at a plurality of examining steps including an examining step of setting a length of a measurement region in a wiring direction to at least 10 times a wire width to measure the wire width and an examining step of examining the wire width, a function (a data analyzing unit) of generating a prediction model of electric characteristic or working size of a semiconductor device using the examination data to generate a control model from the prediction model, and a function (a process control unit) of properly controlling processing conditions for a control process based upon examination data of the plurality of examining steps in the manufacturing process of a semiconductor device and the control model is realized.
摘要翻译：本发明提供一种能够降低半导体装置的电气特性和工作尺寸的波动的半导体装置的制造技术，能够高质量，高产率地制造半导体装置。在半导体器件制造系统中，具有在多个检查步骤中收集检查数据的功能（数据收集单元）的半导体器件的制造过程的控制方法包括将测量区域的长度设置在布线方向为线宽的至少10倍以测量线宽度和检查线宽度的检查步骤，产生半导体器件的电特性或工作尺寸的预测模型的功能（数据分析单元），其使用根据预测模型生成控制模型的检查数据和根据半导体装置的制造过程中的多个检查步骤的检查数据适当地控制用于控制处理的处理条件的功能（过程控制单元），以及实现了控制模型。

7. 发明授权

US08955579B2 Plasma processing apparatus and plasma processing method 有权
标题翻译：等离子体处理装置和等离子体处理方法
公开(公告)号：US08955579B2
公开(公告)日：2015-02-17
申请号：US13091770
申请日：2011-04-21
申请人： Takumi Tandou , Kenetsu Yokogawa , Masaru Izawa
发明人： Takumi Tandou , Kenetsu Yokogawa , Masaru Izawa
IPC分类号： F28D15/00 , F25D23/12 , F25B39/02 , H01L21/336 , H01L21/24 , H01L21/40 , C23C16/00 , H01L21/67
CPC分类号： F25B39/02 , F28F2210/02 , H01J2237/2001 , H01L21/67109
摘要： There is provided a means for uniformly controlling the in-plane temperature of a semiconductor wafer at high speed in a high heat input etching process. A refrigerant channel structure in a circular shape is formed in a sample stage. Due to a fact that a heat transfer coefficient of a refrigerant is largely changed from a refrigerant supply port to a refrigerant outlet port, the cross sections of the channel structure is structured so as to be increased from a first channel areas towards a second channel areas in order to make the heat transfer coefficient of the refrigerant constant in the refrigerant channel structure. Thereby, the heat transfer coefficient of the refrigerant is prevented from increasing by reducing the flow rate of the refrigerant at a dry degree area where the heat transfer coefficient of the refrigerant is increased. Further, the cross section of the channel structure is structured so as to be reduced from the second channel areas towards a third channel areas, and thereby the heat transfer coefficient of the refrigerant is prevented from decreasing. Accordingly, the heat transfer coefficient of the refrigerant can be uniformed in the channel structure.
摘要翻译：提供了一种用于在高热输入蚀刻工艺中高速均匀地控制半导体晶片的面内温度的装置。在样品台中形成圆形的制冷剂流路结构。由于制冷剂的传热系数从制冷剂供给口向制冷剂排出口发生很大的变化，所以，通道结构的横截面被构造成从第一通道区域向第二通道区域以使制冷剂流路结构中的制冷剂的传热系数恒定。因此，通过降低制冷剂的传热系数增加的干燥区域的制冷剂的流量，可以防止制冷剂的传热系数增加。此外，通道结构的横截面被构造成从第二通道区域朝向第三通道区域减小，从而防止制冷剂的传热系数降低。因此，制冷剂的传热系数可以在通道结构中均匀化。

8. 发明申请

US20130112669A1 HEAT TREATMENT APPARATUS 审中-公开
标题翻译：热处理设备
公开(公告)号：US20130112669A1
公开(公告)日：2013-05-09
申请号：US13354358
申请日：2012-01-20
申请人： Takashi UEMURA , Kenetsu Yokogawa , Masatoshi Miyake , Masaru Izawa , Satoshi Sakai
发明人： Takashi UEMURA , Kenetsu Yokogawa , Masatoshi Miyake , Masaru Izawa , Satoshi Sakai
IPC分类号： B23K9/00
CPC分类号： H01J37/32082
摘要： The present invention provides a heat treatment apparatus which can reduce a surface roughing of a processed substrate while keeping a heat efficiency high, even in the case of heating a sample to be heated to 1200° C. or higher. The present invention is a heat treatment apparatus carrying out a heat treatment of a sample to be heated, wherein a plasma generated by a glow electric discharge is used as a heating source, and the sample to be heated is indirectly heated.
摘要翻译：本发明提供一种热处理装置，即使在将待加热的样品加热至1200℃以上的情况下，也能够在保持热效率高的同时降低加工基板的表面粗糙化。本发明是一种对待加热样品进行热处理的热处理装置，其中通过辉光放电产生的等离子体被用作加热源，被加热物被间接加热。

9. 发明授权

US08397668B2 Plasma processing apparatus 有权
公开(公告)号：US08397668B2
公开(公告)日：2013-03-19
申请号：US12398226
申请日：2009-03-05
申请人： Hiroyuki Kobayashi , Kenji Maeda , Kenetsu Yokogawa , Masaru Izawa , Tadamitsu Kanekiyo
发明人： Hiroyuki Kobayashi , Kenji Maeda , Kenetsu Yokogawa , Masaru Izawa , Tadamitsu Kanekiyo
IPC分类号： C23C16/455 , C23C16/50 , C23C16/503 , C23C16/505 , C23C16/509 , C23F1/00 , H01L21/306 , C23C16/06 , C23C16/22
CPC分类号： H01J37/32449 , C23C16/455 , C23C16/50 , C23C16/503 , C23C16/505 , C23C16/509 , H01J37/32082 , H01J37/3244 , H01L21/3065 , Y10T137/0402
摘要： The object of the invention is to provide a plasma processing apparatus having enhanced plasma processing uniformity. The plasma processing apparatus comprises a processing chamber 1, means 13 and 14 for supplying processing gas into the processing chamber, evacuation means 25 and 26 for decompressing the processing chamber 1, an electrode 4 on which an object 2 to be processed such as a wafer is placed, and an electromagnetic radiation power supply 5A, wherein at least two kinds of processing gases having different composition ratios of O2 or N2 are introduced into the processing chamber through different gas inlets so as to control the in-plane uniformity of the critical dimension while maintaining the in-plane uniformity of the process depth.

10. 发明申请

US20120211163A1 PLASMA PROCESSING APPARATUS INCLUDING ETCHING PROCESSING APPARATUS AND ASHING PROCESSING APPARATUS AND PLASMA PROCESSING METHOD USING PLASMA PROCESSING APPARATUS 失效
标题翻译：等离子体处理装置，其中包括蚀刻加工装置和使用等离子体加工装置的匀浆加工装置和等离子体处理方法
公开(公告)号：US20120211163A1
公开(公告)日：2012-08-23
申请号：US13457082
申请日：2012-04-26
申请人： Hiroyuki KOBAYASHI , Masaru Izawa
发明人： Hiroyuki KOBAYASHI , Masaru Izawa
IPC分类号： C23F1/08
CPC分类号： H01J37/32642 , H01J37/32623 , H01J2237/335 , H01L21/67207 , H01L21/68735 , H01L21/68785 , Y10S156/915
摘要： A diameter of a mounting unit of the stage of an ashing processing apparatus is less than a diameter of a mounting unit of the stage of an etching processing apparatus, and the diameter of the mounting unit of the stage of the etching processing apparatus is less than a diameter of an objective item.
摘要翻译：灰化处理装置的台的安装单元的直径小于蚀刻处理装置的台的安装单元的直径，并且蚀刻处理装置的台的安装单元的直径小于客观物品的直径。

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