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1. 发明授权

US11621325B2 Source or drain structures with low resistivity 有权
公开(公告)号：US11621325B2
公开(公告)日：2023-04-04
申请号：US16368097
申请日：2019-03-28
申请人： Intel Corporation
发明人： Cory Bomberger , Anand Murthy , Suresh Vishwanath
IPC分类号： H01L29/08 , H01L21/02 , H01L21/8234 , H01L23/00 , H01L27/088 , H01L29/06 , H01L29/16 , H01L29/66 , H01L29/78 , B82Y10/00 , H01L29/161 , H01L29/165 , H01L29/775 , H01L21/40 , H01L29/417 , H01L27/092 , H01L29/36
摘要： Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

2. 发明授权

US10886145B2 Production of a multi-chip component 有权
公开(公告)号：US10886145B2
公开(公告)日：2021-01-05
申请号：US16072993
申请日：2017-01-26
申请人： OSRAM Opto Semiconductors GmbH
发明人： Michael Zitzlsperger , Tobias Gebuhr , Stephan Eicher
IPC分类号： H01L21/40 , H01L23/495 , H01L21/48 , H01L23/00 , H01L23/31 , H01L33/62 , H01L33/52 , H01L21/56 , H01L33/00 , H01L33/48 , H01L25/075
摘要： A method of producing a surface-mountable multi-chip component includes providing a chip arrangement including a metallic conductor structure exposed at a rear side, a plurality of semiconductor chips and an housing material; and forming a solder stop coating on a rear side of the chip arrangement, wherein the solder stop coating separates connection regions of the conductor structure.

3. 发明授权

US10636875B1 Localized tunneling enhancement for semiconductor devices 有权
公开(公告)号：US10636875B1
公开(公告)日：2020-04-28
申请号：US16252932
申请日：2019-01-21
申请人： Yeong-Chang Chou , Hsu-Hwei Chen , Hui Ma , Thomas R. Young , Youngmin Kim , Jansen J. Uyeda
发明人： Yeong-Chang Chou , Hsu-Hwei Chen , Hui Ma , Thomas R. Young , Youngmin Kim , Jansen J. Uyeda
IPC分类号： H01L29/08 , H01L29/20 , H01L29/45 , H01L29/66 , H01L29/778 , H01L21/38 , H01L21/40 , H01L21/24 , H01L29/207
CPC分类号： H01L29/0895 , H01L29/0843 , H01L29/207 , H01L29/452 , H01L29/66462 , H01L29/7787 , H01L21/24 , H01L21/38 , H01L21/40
摘要： A semiconductor device includes a plurality of base layers. A tunneling layer is disposed on the plurality of base layers. A contact layer is disposed on the tunneling layer. An alloyed metal contact is annealed on to the contact layer. The alloyed metal contact forms a first region and a second region in the contact layer. The first region of the contact layer diffuses into the tunneling layer. The second region of the contact layer resides over the tunneling layer. The tunneling layer facilitates electron mobility of the second region.

4. 发明申请

US20180277392A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180277392A1
公开(公告)日：2018-09-27
申请号：US15991080
申请日：2018-05-29
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Yuhei SATO , Keiji SATO , Tetsunori MARUYAMA , Junichi KOEZUKA
IPC分类号： H01L21/40 , H01L21/324 , H01L29/66 , H01L21/02 , H01L29/786 , H01L21/383 , H01L21/477 , H01L27/12
CPC分类号： H01L21/40 , H01L21/02175 , H01L21/02252 , H01L21/02565 , H01L21/02636 , H01L21/02664 , H01L21/324 , H01L21/383 , H01L21/477 , H01L27/1225 , H01L29/66742 , H01L29/66969 , H01L29/7869
摘要： In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.

5. 发明授权

US08778714B2 Gas sensitive materials for gas detection and methods of making 有权
标题翻译：用于气体检测的气体敏感材料和制造方法
公开(公告)号：US08778714B2
公开(公告)日：2014-07-15
申请号：US13622310
申请日：2012-09-18
申请人： Leonid Israilevich Trakhtenberg , Genrikh Nikolaevich Gerasimov , Vladimir Fedorovich Gromov , Valeriya Isaakovna Rozenberg
发明人： Leonid Israilevich Trakhtenberg , Genrikh Nikolaevich Gerasimov , Vladimir Fedorovich Gromov , Valeriya Isaakovna Rozenberg
IPC分类号： H01L21/40 , B05D5/12
CPC分类号： G01N27/12 , G01N27/127
摘要： A gas sensitive material comprising SnO2 nanocrystals doped with In2O3 and an oxide of a platinum group metal, and a method of making the same. The platinum group metal is preferably Pd, but also may include Pt, Ru, Ir, and combinations thereof. The SnO2 nanocrystals have a specific surface of 7 or greater, preferably about 20 m2/g, and a mean particle size of between about 10 nm and about 100 nm, preferably about 40 nm. A gas detection device made from the gas sensitive material deposited on a substrate, the gas sensitive material configured as a part of a current measuring circuit in communication with a heat source.
摘要翻译：包含掺杂有In 2 O 3的SnO 2纳米晶体和铂族金属的氧化物的气敏材料及其制造方法。铂族金属优选为Pd，但也可以包括Pt，Ru，Ir及其组合。 SnO 2纳米晶体的比表面积为7或更大，优选约20m 2 / g，平均粒度为约10nm至约100nm，优选约40nm。一种由沉积在基底上的气敏材料制成的气体检测装置，气敏材料被配置为与热源连通的电流测量电路的一部分。

6. 发明授权

US08765603B2 Method of forming a buffer layer 有权
标题翻译：形成缓冲层的方法
公开(公告)号：US08765603B2
公开(公告)日：2014-07-01
申请号：US13195554
申请日：2011-08-01
申请人： Cheng-Hao Hou , Wei-Yang Lee , Xiong-Fei Yu , Kuang-Yuan Hsu
发明人： Cheng-Hao Hou , Wei-Yang Lee , Xiong-Fei Yu , Kuang-Yuan Hsu
IPC分类号： H01L21/44 , H01L21/441 , H01L21/40
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/4966 , H01L29/7833
摘要： Buffer layer and method of forming the buffer layer, the method including forming a high-k dielectric layer, forming a titanium nitride layer over the high-k dielectric layer, forming a silicon layer on the titanium nitride layer, annealing the silicon layer into the titanium nitride layer to form an annealed silicon layer and forming an n-metal over the high-k dielectric layer.
摘要翻译：缓冲层和形成缓冲层的方法，所述方法包括形成高k电介质层，在高k电介质层上形成氮化钛层，在氮化钛层上形成硅层，将硅层退火成氮化钛层以形成退火的硅层，并在高k电介质层上形成n金属。

7. 发明授权

US08686572B2 Apparatus for stacking integrated circuits 有权
标题翻译：用于堆叠集成电路的装置
公开(公告)号：US08686572B2
公开(公告)日：2014-04-01
申请号：US13720849
申请日：2012-12-19
申请人： Stec, Inc.
发明人： Mark Moshayedi
IPC分类号： H01L21/40 , H05K7/00
CPC分类号： H05K1/181 , H01L23/50 , H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H05K1/141 , H05K1/144 , H05K1/182 , H05K3/3442 , H05K2201/049 , H05K2201/09072 , H05K2201/0949 , H05K2201/10515 , H05K2201/10666 , H05K2201/10689 , H01L2924/00
摘要： A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.
摘要翻译：多芯片堆叠模块为给定的表面芯片占用空间提供了增加的电路密度。支撑结构与标准表面贴装型芯片交替形成堆叠，其中支撑结构将芯片电互连。一个方面是用于在垂直堆叠中互连多个大致平面的芯片的结构和方法，使得在堆叠中共同连接的芯片的信号和单独访问的信号在堆栈内分离。

8. 发明授权

US08673681B2 Electrical device fabrication 有权
标题翻译：电气设备制造
公开(公告)号：US08673681B2
公开(公告)日：2014-03-18
申请号：US12296772
申请日：2007-04-11
申请人： Kate Jessie Stone
发明人： Kate Jessie Stone
IPC分类号： H01L21/40 , H01L21/22 , H01L21/38 , H01L21/20 , H01L21/302
CPC分类号： H05K3/061 , H01L51/0022 , H01L51/0541 , H01L51/102 , H01L51/441 , H01L51/5206 , H01L51/5221 , H05K3/0079 , H05K2203/0143 , Y02E10/549
摘要： The invention provides a method of making an electrical device, particularly a semiconductor device, having a substrate and etched electrodes formed on the substrate. The method employs flexography to print a resist pattern (7) onto a substrate (5) carrying a metal layer (8). Metal not protected by the resist can be etched away and then the resist (7) removed to leave exposed electrodes. Further materials (10, 11) can be disposed onto the exposed metal, such as organic semiconductors, to form transistors or diodes.
摘要翻译：本发明提供一种制造具有衬底和形成在衬底上的蚀刻电极的电子器件，特别是半导体器件的方法。该方法使用柔性版印刷将抗蚀剂图案（7）印刷到承载金属层（8）的基底（5）上。不被抗蚀剂保护的金属可以被蚀刻掉，然后去除抗蚀剂（7）以留下暴露的电极。另外的材料（10,11）可以设置在诸如有机半导体的暴露的金属上，以形成晶体管或二极管。

9. 发明授权

US08484820B2 Semiconductor device fabricating method and fabricating apparatus 有权
公开(公告)号：US08484820B2
公开(公告)日：2013-07-16
申请号：US13067804
申请日：2011-06-28
申请人： Yoshihiro Saeki
发明人： Yoshihiro Saeki
IPC分类号： B25B11/00 , B25B1/00 , B25B27/14 , B23Q3/00 , H01L21/44 , H01L21/00 , H01L21/40
CPC分类号： H01L24/75 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2224/75 , H01L2224/75301 , H01L2224/75745 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , Y10T29/53178 , Y10T29/53961 , H01L2224/05599
摘要： Respective attracting openings of a bonding head are disposed so as to avoid joining regions at which bump electrodes (obverse electrodes) of a semiconductor chip are joined with bump electrodes of a package substrate. Bump electrodes (reverse electrodes) that are connected to the bump electrodes are provided at a reverse side of the semiconductor chip at positions opposing the bump electrodes. Because the attracting openings do not overlap the joining regions, the bump electrodes (reverse electrodes) are not suctioned at the joining regions.

10. 发明授权

US07982281B2 Method of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI device 有权
标题翻译：制造半导体器件的方法，制造SOI器件的方法，半导体器件和SOI器件
公开(公告)号：US07982281B2
公开(公告)日：2011-07-19
申请号：US11828268
申请日：2007-07-25
申请人： Gabriel Dehlinger
发明人： Gabriel Dehlinger
IPC分类号： H01L21/40
CPC分类号： H01L21/84 , H01L21/743
摘要： According to one embodiment of the present invention, a SOI device includes a first composite structure including a substrate layer, a substrate isolation layer being disposed on or above the substrate layer, a buried layer being disposed on or above the substrate isolation layer, and a semiconductor layer being disposed on or above the buried layer; a trench structure being formed within the first composite structure; and a second composite structure provided on the side walls of the trench structure, wherein the second composite structure includes a first isolation layer covering the part of the side walls formed by the semiconductor layer and formed by an upper part of the buried layer; and a contact layer covering the isolation layer and the part of the side walls formed by a lower part of the buried layer.
摘要翻译：根据本发明的一个实施例，SOI器件包括第一复合结构，其包括衬底层，衬底隔离层设置在衬底层上或衬底上，掩埋层设置在衬底隔离层上或上方，以及半导体层设置在掩埋层上或上方; 在第一复合结构内形成沟槽结构; 以及设置在所述沟槽结构的侧壁上的第二复合结构，其中所述第二复合结构包括覆盖由所述半导体层形成并由所述掩埋层的上部形成的所述侧壁的所述一部分的第一隔离层; 以及覆盖隔离层和由埋层的下部形成的侧壁的一部分的接触层。

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