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1. 发明申请

US20180052106A1 DUAL DETECTION SCHEME FOR DNA SEQUENCING 审中-公开
公开(公告)号：US20180052106A1
公开(公告)日：2018-02-22
申请号：US15239032
申请日：2016-08-17
申请人： Kerry Gunning , Donald Ackley , Chan-Long Shieh
发明人： Kerry Gunning , Donald Ackley , Chan-Long Shieh
IPC分类号： G01N21/64 , C12Q1/68 , G01N27/414
CPC分类号： G01N21/6428 , C12Q1/6869 , G01N27/4145 , G01N2021/6439 , G01N2201/062 , C12Q2563/107 , C12Q2565/607
摘要： Apparatus for fluorescent and ion sensing of DNA nucleotide incorporation events including DNA nucleotide incorporation structure designed to have sequencing primers bonded to a surface for the incorporation of DNA nucleotides thereon. At least some of the DNA nucleotides having a fluorescent label. A photodiode positioned adjacent the incorporation structure and an illumination device positioned adjacent the DNA nucleotide incorporation structure to illuminate DNA nucleotides incorporated onto the sequencing primers. The illumination device exciting the fluorescent labels when incorporation occurs and the photodiode positioned to sense the excited fluorescent labels. Ion sensing apparatus positioned adjacent the DNA nucleotide incorporation structure including a metal oxide thin film transistor with a gate electrically coupled to receive an electrical signal indicative of ion emissions produced by the DNA nucleotide incorporated onto DNA target fragments or sequencing primers.

2. 发明授权

US06203981B1 Transistor-based molecular detection apparatus and method 失效
标题翻译：基于晶体管的分子检测装置及方法
公开(公告)号：US06203981B1
公开(公告)日：2001-03-20
申请号：US09068172
申请日：1999-02-08
申请人： Donald Ackley , Chan-Long Shieh , Thomas B. Harvey, III
发明人： Donald Ackley , Chan-Long Shieh , Thomas B. Harvey, III
IPC分类号： C12Q168
CPC分类号： G01N33/5438 , B01J2219/00605 , B01J2219/0061 , B01J2219/00612 , B01J2219/00653 , B01J2219/00659 , G01N27/4145
摘要： Adjacent first and second transistors are integrated with a substrate. Each of the first and second transistors has a gate electrode, a source electrode, a drain electrode and a semiconductive channel formed of an organic material, the semiconductive channel electrically coupling the source electrode with the drain electrode. The source electrode of the first transistor is electrically coupled to the source electrode of the second transistor. A molecular receptor is bound directly to a surface of the semiconductive channel of the first transistor. A non-zero offset voltage, which produces equal channel currents in the semiconductive channels of the first and second transistors after a molecule has bound with the molecular receptor without a like binding event proximate to the second transistor, is sensed between the gate electrodes of the first and second transistors.
摘要翻译：相邻的第一和第二晶体管与衬底集成。第一和第二晶体管中的每一个具有栅电极，源电极，漏电极和由有机材料形成的半导体沟道，半导体沟道将源电极与漏电极电耦合。第一晶体管的源电极电耦合到第二晶体管的源电极。分子受体直接结合到第一晶体管的半导体通道的表面。在零分子与分子受体结合而没有靠近第二晶体管的相似结合事件之后，在第一和第二晶体管的半导体通道中产生相等的沟道电流的非零偏移电压被感测在第一和第二晶体管。

3. 发明授权

US09911857B2 Thin film transistor with low trap-density material abutting a metal oxide active layer and the gate dielectric 有权
公开(公告)号：US09911857B2
公开(公告)日：2018-03-06
申请号：US12915712
申请日：2010-10-29
申请人： Chan-Long Shieh , Fatt Foong , Gang Yu
发明人： Chan-Long Shieh , Fatt Foong , Gang Yu
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L29/78696
摘要： A metal oxide semiconductor device including an active layer of metal oxide, a layer of gate dielectric, and a layer of low trap density material. The layer of low trap density material is sandwiched between the active layer of metal oxide and the layer of gate dielectric. The layer of low trap density material has a major surface parallel and in contact with a major surface of the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide. A second layer of low trap density material can optionally be placed in contact with the opposed major surface of the active layer of metal oxide so that a low trap density interface is formed with both surfaces of the active layer of metal oxide.

4. 发明授权

US09773824B2 Active matrix light emitting diode array and projector display comprising it 有权
公开(公告)号：US09773824B2
公开(公告)日：2017-09-26
申请号：US15087716
申请日：2016-03-31
申请人： Chan-Long Shieh , Gang Yu
发明人： Chan-Long Shieh , Gang Yu
IPC分类号： H01L27/146 , H01L27/12 , H01L33/00 , H01L33/44 , H01L33/46 , H01L33/62 , H01L33/64 , H01L27/15
CPC分类号： H01L27/14609 , H01L27/1225 , H01L27/1248 , H01L27/1262 , H01L27/14603 , H01L27/1463 , H01L27/14663 , H01L27/14692 , H01L27/156 , H01L33/0075 , H01L33/44 , H01L33/46 , H01L33/62 , H01L33/642 , H01L2933/0025 , H01L2933/0033 , H01L2933/0066 , H01L2933/0075
摘要： A method of fabricating a pixelated imager and structure including a substrate with a bottom contact layer and active element blanket layers deposited on the bottom contact layer. The blanket layers are separated into an array of active elements with trenches isolating adjacent active elements in the array. A dielectric passivation/planarization layer is positioned over the array of active elements. An array of active element readout circuits overlies the passivation/planarization layer above the trenches with one active element readout circuit coupled to each active element of the array of active elements. Each active element and coupled active element readout circuit defines a pixel and the array of active elements and the coupled array of active element readout circuits defines a pixelated imager, and the readout circuit coupled to each active element includes at least one TFT with an active channel comprising a metal-oxide semiconductor material.

5. 发明授权

US09614102B2 Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption 有权
公开(公告)号：US09614102B2
公开(公告)日：2017-04-04
申请号：US15080231
申请日：2016-03-24
申请人： Chan-Long Shieh , Gang Yu , Fatt Foong
发明人： Chan-Long Shieh , Gang Yu , Fatt Foong
IPC分类号： H01L29/786 , H01L27/12 , H01L29/66 , H01L21/70 , H01L21/02
CPC分类号： H01L29/78696 , H01L21/02554 , H01L21/02565 , H01L21/707 , H01L27/1225 , H01L27/124 , H01L27/1288 , H01L29/66969 , H01L29/78606 , H01L29/7869
摘要： A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

6. 发明申请

US20160293769A1 HIGH MOBILITY STABILE METAL OXIDE TFT 审中-公开
标题翻译：高移动性稳定的金属氧化物薄膜
公开(公告)号：US20160293769A1
公开(公告)日：2016-10-06
申请号：US15186628
申请日：2016-06-20
申请人： Chan-Long Shieh , Gang Yu , Fatt Foong , Tian Xiao , Juergen Musolf
发明人： Chan-Long Shieh , Gang Yu , Fatt Foong , Tian Xiao , Juergen Musolf
IPC分类号： H01L29/786 , H01L23/535 , H01L21/467 , H01L29/66 , H01L21/4763 , H01L29/417 , H01L29/06
CPC分类号： H01L29/7869 , H01L21/467 , H01L21/4763 , H01L23/535 , H01L29/0649 , H01L29/41733 , H01L29/66969 , H01L29/78696
摘要： A method of fabricating a stable, high mobility metal oxide thin film transistor includes the steps of providing a substrate, positioning a gate on the substrate, and depositing a gate dielectric layer on the gate and portions of the substrate not covered by the gate. A multiple film active layer including a metal oxide semiconductor film and a metal oxide passivation film is deposited on the gate dielectric with the passivation film positioned in overlying relationship to the semiconductor film. An etch-stop layer is positioned on a surface of the passivation film and defines a channel area in the active layer. A portion of the multiple film active layer on opposite sides of the etch-stop layer is modified to form an ohmic contact and metal source/drain contacts are positioned on the modified portion of the multiple film active layer.
摘要翻译：一种制造稳定的高迁移率金属氧化物薄膜晶体管的方法包括以下步骤：提供衬底，将栅极定位在衬底上，以及在栅极上沉积栅极电介质层，并且将衬底部分未被栅极覆盖。包括金属氧化物半导体膜和金属氧化物钝化膜的多层膜活性层沉积在栅极电介质上，钝化膜位于与半导体膜的重叠关系中。蚀刻停止层位于钝化膜的表面上并限定有源层中的沟道区。在蚀刻停止层的相对侧上的多个膜有源层的一部分被修改以形成欧姆接触，并且金属源极/漏极触点位于多个膜有源层的修改部分上。

7. 发明授权

US09362413B2 MOTFT with un-patterned etch-stop 有权
标题翻译：具有未图案化蚀刻停止的MOTFT
公开(公告)号：US09362413B2
公开(公告)日：2016-06-07
申请号：US14081130
申请日：2013-11-15
申请人： Gang Yu , Chan-Long Shieh , Juergen Musolf , Fatt Foong , Tian Xiao
发明人： Gang Yu , Chan-Long Shieh , Juergen Musolf , Fatt Foong , Tian Xiao
IPC分类号： H01L29/786 , H01L29/24 , H01L21/02 , H01L29/66
CPC分类号： H01L27/1203 , H01L21/02565 , H01L21/02664 , H01L29/24 , H01L29/66969 , H01L29/7869
摘要： A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.
摘要翻译：一种制造高迁移率半导体金属氧化物薄膜晶体管的方法，包括以下步骤：沉积半导体金属氧化物材料层，在MO材料层上沉积蚀刻停止材料的覆盖层，以及图案化源/漏层包括将源极/漏极金属层蚀刻成定位成限定半导体金属氧化物层中的沟道区域的源极/漏极端子的蚀刻停止材料的覆盖层上的金属。蚀刻停止材料至少在源极/漏极端子之下在垂直于覆盖层的平面的方向上导电，以在源极/漏极端子和半导体金属氧化物材料层之间提供电接触。蚀刻停止材料也是化学稳固的，以在蚀刻工艺期间保护半导体金属氧化物沟道材料层。

8. 发明授权

US09318614B2 Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption 有权
标题翻译：自对准金属氧化物TFT，具有减少数量的掩模并降低功耗
公开(公告)号：US09318614B2
公开(公告)日：2016-04-19
申请号：US14071644
申请日：2013-11-05
申请人： Chan-Long Shieh , Gang Yu , Fatt Foong
发明人： Chan-Long Shieh , Gang Yu , Fatt Foong
IPC分类号： H01L21/00 , H01L29/786 , H01L27/12 , H01L29/66 , H01L21/70 , H01L21/02
CPC分类号： H01L29/78696 , H01L21/02554 , H01L21/02565 , H01L21/707 , H01L27/1225 , H01L27/124 , H01L27/1288 , H01L29/66969 , H01L29/78606 , H01L29/7869
摘要： A method of fabricating MOTFTs includes positioning opaque gate metal on a transparent substrate, depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Etch stop material is deposited on the semiconductor material. Photoresist defines an isolation area in the semiconductor material. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
摘要翻译：制造MOTFT的方法包括将不透明栅极金属定位在透明基板上，沉积覆盖栅极金属的栅介质材料和周围区域，以及在其上沉积金属氧化物半导体材料。蚀刻停止材料沉积在半导体材料上。光致抗蚀剂界定半导体材料中的隔离区。从基板的后表面露出光致抗蚀剂，除去暴露的部分以使蚀刻停止材料未被覆盖，除了覆盖并与栅极金属对准的部分之外。蚀刻半导体材料的未覆盖部分以隔离TFT。使用光致抗蚀剂，选择性地蚀刻蚀刻停止层以留下覆盖并与栅极金属对准的部分并限定半导体材料中的沟道区域。沉积和图案化导电材料以形成源区和漏区。

9. 发明授权

US09117918B2 Metal oxide TFT with improved source/drain contacts 有权
标题翻译：具有改善的源极/漏极触点的金属氧化物TFT
公开(公告)号：US09117918B2
公开(公告)日：2015-08-25
申请号：US14175521
申请日：2014-02-07
申请人： Chan-Long Shieh , Gang Yu , Fatt Foong
发明人： Chan-Long Shieh , Gang Yu , Fatt Foong
IPC分类号： H01L29/786 , H01L21/428 , H01L29/45 , H01L29/66
CPC分类号： H01L29/7869 , H01L21/428 , H01L29/45 , H01L29/66969 , H01L29/78606
摘要： A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
摘要翻译：在金属氧化物半导体薄膜晶体管中形成欧姆源极/漏极接触的方法包括：提供栅极，栅极电介质，具有带隙的高载流子浓度金属氧化物半导体有源层和间隔开的源/漏极金属接触体薄膜晶体管配置。间隔开的源极/漏极金属触点限定有源层中的沟道区。在沟道区域附近提供氧化环境，并且栅极和沟道区域在氧化环境中被加热以降低沟道区域中的载流子浓度。或者或另外每个源极/漏极触点包括位于金属氧化物半导体有源层上的非常薄的低功函数金属层，并且高功函数金属的势垒层位于低功函数金属上。

10. 发明授权

US09070779B2 Metal oxide TFT with improved temperature stability 有权
标题翻译：具有改善温度稳定性的金属氧化物TFT
公开(公告)号：US09070779B2
公开(公告)日：2015-06-30
申请号：US13718183
申请日：2012-12-18
申请人： Chan-Long Shieh , Fatt Foong , Juergen Musolf , Gang Yu
发明人： Chan-Long Shieh , Fatt Foong , Juergen Musolf , Gang Yu
IPC分类号： H01L29/66 , H01L29/786
CPC分类号： H01L29/7869 , H01L29/66969 , H01L29/78696
摘要： A metal oxide thin film transistor includes a metal oxide semiconductor channel with the metal oxide semiconductor having a conduction band with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band with a second energy level equal to, or less than 0.5 eV above the first energy level.
摘要翻译：金属氧化物薄膜晶体管包括金属氧化物半导体沟道，金属氧化物半导体具有具有第一能级的导带。晶体管还包括覆盖金属氧化物半导体沟道的至少一部分的钝化材料层。钝化材料具有等于或小于第一能级高于0.5eV的第二能级的导带。

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