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1. 发明授权

US06709974B2 Method of preventing seam defects in isolated lines 有权
标题翻译：防止隔离线缝合缺陷的方法
公开(公告)号：US06709974B2
公开(公告)日：2004-03-23
申请号：US10322763
申请日：2002-12-19
申请人： David Permana , Jiong-Ping Lu , Albert Cheng , Jeff A. West , Brock W. Fairchild , Scott A. Johannesmeyer , Chris M. Bowles , Thomas D. Bonifield , Rajesh Tiwari
发明人： David Permana , Jiong-Ping Lu , Albert Cheng , Jeff A. West , Brock W. Fairchild , Scott A. Johannesmeyer , Chris M. Bowles , Thomas D. Bonifield , Rajesh Tiwari
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/3212 , H01L21/7684
摘要： A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.
摘要翻译：提供了一种在CMP工艺期间防止0.3微米或更小的狭窄隔离线上的接缝缺陷的方法。解决方案是改变与金属层相同的层上的虚拟金属结构的特征的尺寸，以使其宽度为约0.6微米或更小，使得在电镀期间，特征中的沉积速率类似于窄的，隔离的线条。虚拟金属结构的密度，形状和接近度通过防止电蚀腐蚀来防止CMP加工过程中的接缝缺陷。

2. 发明授权

US07199032B2 Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing 有权
标题翻译：金属硅化物通过硅<110>通道填料引起横向过度侵蚀
公开(公告)号：US07199032B2
公开(公告)日：2007-04-03
申请号：US10903319
申请日：2004-07-30
申请人： Duofeng Yue , Peijun J. Chen , Sue Ellen Crank , Thomas D. Bonifield , Jiong-Ping Lu , Jie-Jie Xu
发明人： Duofeng Yue , Peijun J. Chen , Sue Ellen Crank , Thomas D. Bonifield , Jiong-Ping Lu , Jie-Jie Xu
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L29/6659
摘要： The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).
摘要翻译：本发明提供一种制造用于半导体器件（110）的金属硅化物电极（100）的方法。该方法包括将小原子注入nMOS半导体衬底（130）至nMOS半导体衬底中不大于约30纳米的深度（132）。该方法还包括在nMOS半导体衬底上沉积过渡金属层（400）。使过渡金属层和nMOS半导体衬底反应以形成金属硅化物电极。本发明的其它方面包括制造集成电路（700）的方法。

3. 发明申请

US20050186788A1 System for improving thermal stability of copper damascene structure 审中-公开
公开(公告)号：US20050186788A1
公开(公告)日：2005-08-25
申请号：US11090103
申请日：2005-03-24
申请人： Jiong-Ping Lu , Qi-Zhong Hong , Tz-Cheng Chiu , Changming Jin , David Permana , Ting Tsui
发明人： Jiong-Ping Lu , Qi-Zhong Hong , Tz-Cheng Chiu , Changming Jin , David Permana , Ting Tsui
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76877 , H01L21/76883
摘要： Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.

4. 发明授权

US06903000B2 System for improving thermal stability of copper damascene structure 有权
标题翻译：提高铜镶嵌结构热稳定性的系统
公开(公告)号：US06903000B2
公开(公告)日：2005-06-07
申请号：US10114778
申请日：2002-04-03
申请人： Jiong-Ping Lu , Qi-Zhong Hong , Tz-Cheng Chiu , Changming Jin , David Permana , Ting Tsui
发明人： Jiong-Ping Lu , Qi-Zhong Hong , Tz-Cheng Chiu , Changming Jin , David Permana , Ting Tsui
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76877 , H01L21/76883
摘要： Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112) is deposited over the interconnect structure (110). The interconnect structure (110) is annealed with the overlying cap (112) in place. The cap (112) is then removed after the interconnect structure (110) is annealed.
摘要翻译：公开了一种用于制造半导体器件（100）的系统。互连结构（110）形成在半导体器件（100）上，并且帽（112）沉积在互连结构（110）上。互连结构（110）与上覆盖（112）退火就位。然后在互连结构（110）退火之后去除盖（112）。

5. 发明授权

US06583053B2 Use of a sacrificial layer to facilitate metallization for small features 有权
公开(公告)号：US06583053B2
公开(公告)日：2003-06-24
申请号：US09816436
申请日：2001-03-23
申请人： Jiong-Ping Lu , Changming Jin , David Permana
发明人： Jiong-Ping Lu , Changming Jin , David Permana
IPC分类号： H01L214763
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76838 , H01L21/7684 , H01L21/76843 , H01L21/7688
摘要： A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108) is formed over the SiC layer (106). A trench (112) is etched in the sacrificial layer (108), the SiC layer (106) and the dielectric layer (102). A sputter etch of the sacrificial layer (108) is used to create a wider opening at a top of the sacrificial layer (108) than at a top of the dielectric layer (102). A barrier layer (114) and copper seed layer (116) are formed. The trench (112) is then filled with copper (124). CMP is used to remove the excess copper (124) and barrier layer (114) stopping on the SiC (106).

6. 发明授权

US07994073B2 Low stress sacrificial cap layer 有权
标题翻译：低应力牺牲帽层
公开(公告)号：US07994073B2
公开(公告)日：2011-08-09
申请号：US11940433
申请日：2007-11-15
申请人： Jiong-Ping Lu , Periannan Chidambaram , Srinivasan Chakravarthi
发明人： Jiong-Ping Lu , Periannan Chidambaram , Srinivasan Chakravarthi
IPC分类号： H01L21/31
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译：具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120。或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410.而且，用于制造具有低应力牺牲帽层120,410的晶体管40,400的方法300,500。

7. 发明授权

US07732852B2 High-K dielectric materials and processes for manufacturing them 有权
标题翻译：高K介电材料及其制造方法
公开(公告)号：US07732852B2
公开(公告)日：2010-06-08
申请号：US11499308
申请日：2006-08-03
申请人： Jiong-Ping Lu , Ming-Jang Hwang
发明人： Jiong-Ping Lu , Ming-Jang Hwang
IPC分类号： H01L27/108
CPC分类号： C23C16/34 , C23C16/56 , H01L21/31604 , H01L21/31637 , H01L21/31683 , H01L27/1085 , H01L28/40 , H01L28/57
摘要： High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.
摘要翻译：通过相应氮化物的顺序化学气相沉积（CVD）形成钛和钨或钛和钽的混合过渡金属氧化物的高介电膜，并在氧的存在下退火以致密化和氧化氮化物。所得到的膜可用作电容性电池并且抵抗向下层材料的氧扩散，具有高电容和低电流泄漏。

8. 发明授权

US07666729B2 Method for improving the thermal stability of silicide 有权
标题翻译：改善硅化物热稳定性的方法
公开(公告)号：US07666729B2
公开(公告)日：2010-02-23
申请号：US11456595
申请日：2006-07-11
申请人： Jiong-Ping Lu , Jiejie Xu
发明人： Jiong-Ping Lu , Jiejie Xu
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/28052 , H01L21/265 , H01L21/28518 , H01L21/823835 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface of the gate electrode 110.
摘要翻译：本发明的一个实施例是通过在栅电极层110上执行离子注入来制造晶体管的方法。该方法可以包括在半导体衬底20上形成界面层200并执行退火以在顶部形成硅化物190 栅电极110的表面。

9. 发明授权

US07655555B2 In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliability 有权
标题翻译：在扩散阻挡材料沉积中Si的原位共沉积，具有改善的润湿性，阻隔效率和器件可靠性
公开(公告)号：US07655555B2
公开(公告)日：2010-02-02
申请号：US09895520
申请日：2001-06-28
申请人： Richard A. Faust , Qing-Tang Jiang , Jiong-Ping Lu
发明人： Richard A. Faust , Qing-Tang Jiang , Jiong-Ping Lu
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/28
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/76807 , H01L21/76843
摘要： A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.
摘要翻译：具有过渡金属 - 氮化硅屏障（106）的铜互连。过渡金属氮化物通过在含Si环境中的反应性溅射与Si共沉积以形成势垒（106）。然后，铜（110）以良好的粘附性沉积在过渡金属 - 氮化硅屏障（108）上。

10. 发明授权

US07448395B2 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US07448395B2
公开(公告)日：2008-11-11
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： B08B6/00 , C25F1/00 , C25F3/30 , C25F5/00
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

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