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1. 发明授权

US06463472B1 System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes 有权
标题翻译：用于在具有忙和故障节点的环网系统中维持强顺序排序的分组流的系统
公开(公告)号：US06463472B1
公开(公告)日：2002-10-08
申请号：US09854294
申请日：2001-05-10
申请人： William C. Van Loo
发明人： William C. Van Loo
IPC分类号： G06F1300
CPC分类号： H04L12/40052 , H04L1/1806 , H04L1/1809 , H04L12/40091 , H04L12/42 , H04L12/433
摘要： A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgement for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.
摘要翻译：一种用于在环网中维护可靠的分组分布的系统，其支持强有序的，非重要的命令。网络上的每个消费者节点保持已经通过该节点的分组序列的记录，以及其通过时的每个分组的状态，包括最后一个已知的良好分组的记录及其序列号。当生产者节点检测到分组的确认中的错误状况时，重新发送所有以最后一个已知好的分组开始的分组。每个消费者节点能够处理或拒绝重新发送的分组，包括可能已经被处理的分组，由于所有分组的分组和状态记录，它们知道。

2. 发明授权

US6101565A System for multisized bus coupling in a packet-switched computer system 失效
公开(公告)号：US6101565A
公开(公告)日：2000-08-08
申请号：US912772
申请日：1997-08-18
申请人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
发明人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
IPC分类号： G06F13/36 , G06F13/40 , G06F15/173 , G06F13/00
CPC分类号： G06F13/4018
摘要： A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.

3. 发明授权

US5892957A Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system 失效
标题翻译：用于基于分组交换微处理器的计算机系统中的中断通信的方法和装置
公开(公告)号：US5892957A
公开(公告)日：1999-04-06
申请号：US868171
申请日：1997-06-03
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

4. 发明授权

US5710891A Pipelined distributed bus arbitration system 失效
标题翻译：流水线分布式总线仲裁系统
公开(公告)号：US5710891A
公开(公告)日：1998-01-20
申请号：US414559
申请日：1995-03-31
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
IPC分类号： G06F15/16 , G06F13/368 , G06F13/374 , G06F15/177 , G06F13/00
CPC分类号： G06F13/368 , G06F13/374
摘要： The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration within all the respective bus arbiters occurs in a second clock cycle.
摘要翻译：本发明提供了一种可扩展的，模块化和流水线分布式总线仲裁系统，用于有效地分辨耦合到公共系统总线的子系统（例如处理器）之间的总线争用。仲裁系统包括多个分布式总线仲裁器，其接收来自子系统的总线请求并独立地确定下一个总线主机。仲裁协议使仲裁过程能够从临界定时路径中消除，从而允许系统以给定的集成电路（IC）技术可能的最大系统时钟频率工作，以减少整体系统时钟延迟。在仲裁时钟周期期间，子系统之间的任何改变都是基于任何在仲裁时钟周期之前的时钟周期期间有效的系统总线请求，并且独立于在系统总线请求期间断言的任何系统总线请求仲裁时钟周期。此外，仲裁协议优先处理当前总线主机，即总线主机驱动系统总线。无论处理器速度如何，每个仲裁任务都在系统时钟周期内完成。因此，用于保留当前总线主机的仲裁延迟是一个系统时钟周期，而用于选择和切换总线主机的延迟是两个系统时钟周期。在此实现中，最后一个端口驱动程序是允许在时钟周期内断言总线请求的唯一子系统，并在下一个即时时钟周期内立即驱动系统总线。相反，当不是最后端口驱动器的第二子系统需要驱动非活动系统总线时，第二子系统在第一时钟周期内断言其总线请求线，并且在所有相应的总线仲裁器中进行仲裁发生在第二个时钟周期。

5. 发明授权

US5689713A Method and apparatus for interrupt communication in a packet-switched computer system 失效
标题翻译：分组交换计算机系统中的中断通信的方法和装置
公开(公告)号：US5689713A
公开(公告)日：1997-11-18
申请号：US425537
申请日：1995-04-20
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

6. 发明授权

US5657472A Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor 失效
标题翻译：具有与每个处理器相关联的独立并行事务队列的多处理器系统的内存事务执行系统和方法
公开(公告)号：US5657472A
公开(公告)日：1997-08-12
申请号：US414922
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III , Charles E. Narad
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III , Charles E. Narad
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0828
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for each master class, for transmitting and receiving memory access requests. The system controller further includes memory transaction request logic for processing each memory transaction request and a duplicate cache index having a set of duplicate cache tags (Dtags), including one cache tag corresponding to each master cache tag in an associated data processor.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。每个主缓存索引具有一组主缓存标签（Etags），包括缓存存储器存储的每个数据块的一个缓存标签。每个数据处理器包括主界面，用于向系统控制器发送存储器事务请求，以及从其他数据处理器接收来自系统控制器的对应于存储器事务请求的高速缓存访问请求。在优选实施例中，每个存储器事务请求被分类为两个不同的主类之一：包括读存储器访问请求的第一事务类和包括回写存储器访问请求的第二事务类。主接口和系统控制器具有对应的并行请求队列，每个主类一个，用于发送和接收存储器访问请求。系统控制器还包括用于处理每个存储器事务请求的存储器事务请求逻辑和具有一组重复高速缓存标签（Dtags）的重复高速缓存索引，包括与相关联的数据处理器中的每个主高速缓存标签相对应的一个高速缓存标签。

7. 发明授权

US5581729A Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system 失效
标题翻译：并行相干读写事务处理系统，用于分组交换高速缓存一致多处理器系统
公开(公告)号：US5581729A
公开(公告)日：1996-12-03
申请号：US414763
申请日：1995-03-31
申请人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Paul Loewenstein , Sue K. Lee , Louis F. Coffin III
发明人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Paul Loewenstein , Sue K. Lee , Louis F. Coffin III
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。每个主缓存索引具有一组主缓存标签（Etags），包括缓存存储器存储的每个数据块的一个缓存标签。每个数据处理器包括具有用于向系统控制器发送存储器事务请求的主类的主接口。系统控制器包括用于由数据处理器处理每个存储器事务请求的存储器事务请求逻辑。系统控制器维护具有每个数据处理器的一组重复缓存标签（Dtags）的重复缓存索引。每个数据处理器具有用于存储先前存储在受害高速缓存行中的数据块的回写缓冲器，直到其各自的回写事务完成为止，以及用于存储与先前执行的读取事务相关联的高速缓存行的高速缓存状态的第N + 1个Dtag 到读写回事务对的相关回写事务。因此，在高速缓存未命中时，互连可以依赖于回写缓冲器或Nth + 1Dtag并行地执行读取和回写事务，以适应事务的任何排序。

8. 发明授权

US4271468A Multiprocessor mechanism for handling channel interrupts 失效
公开(公告)号：US4271468A
公开(公告)日：1981-06-02
申请号：US91902
申请日：1979-11-06
申请人： Neal T. Christensen , William C. Van Loo , Robert H. Werner , Joseph A. Wetzel , Carl Zeitler, Jr.
发明人： Neal T. Christensen , William C. Van Loo , Robert H. Werner , Joseph A. Wetzel , Carl Zeitler, Jr.
IPC分类号： G06F13/14 , G06F9/46 , G06F9/48 , G06F13/26 , G06F15/16 , G06F15/177 , G06F15/00
CPC分类号： G06F13/26
摘要： The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program.An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty.A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs.In each CP, acceptance determining circuits connect to the broadcast bus and accept the highest-priority-unmask non-empty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state.Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queue at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP.An inhibit register in the interrupt controller in the SC inhibits selected bits on the broadcast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends its acceptance of the corresponding queue, so that any CP can select the next entry on the corresponding queue.When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state.

9. 发明授权

US06381664B1 System for multisized bus coupling in a packet-switched computer system 有权
标题翻译：在分组交换计算机系统中用于多尺寸总线耦合的系统
公开(公告)号：US06381664B1
公开(公告)日：2002-04-30
申请号：US09597963
申请日：2000-06-20
申请人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
发明人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
IPC分类号： G06F1300
CPC分类号： G06F13/4018
摘要： A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.
摘要翻译：一种用于具有分组交换数据总线的计算机系统的数据传输控制系统，用于控制从具有一个总线宽度的设备到具有不同总线宽度的设备的数据字的传送。第一总线可以是主总线，第二总线是连接到计算机系统并耦合到主总线的诸如存储器或其他设备的功能单元的总线。当第二总线小于第一总线时，数据传输控制系统通过仅将每个时钟周期的部分字传送到第二总线来适应这种情况，有效延迟数据传输到第二总线可以处理的速率。传输速率因子基本上等于第二总线宽度与第一总线宽度的比率。在替代实施例中，数据传输控制系统以给定计算机系统的处理器或时钟速度和主总线的宽度的基本上可利用的全速率传送数据字，并且在传送到第二总线之前缓冲字。然后，传输到缓冲器的速度不受第二总线的大小限制，而仅由缓冲器的大小限制，缓冲器的大小优选地具有至少与母线总线相同的输入总线。该系统可容纳不同尺寸的功能单元，以连接到给定尺寸的主总线，其中不同尺寸可能大于或小于主总线尺寸，因此功能单元可以以最佳总线大小来构建特定功能，而不必符合可能不合适，低效或昂贵或浪费的主总线大小。

10. 发明授权

US06260174B1 Method and apparatus for fast-forwarding slave requests in a packet-switched computer system 有权
标题翻译：用于在分组交换计算机系统中快速转发从请求的方法和装置
公开(公告)号：US06260174B1
公开(公告)日：2001-07-10
申请号：US09179048
申请日：1998-10-26
申请人： William C. Van Loo
发明人： William C. Van Loo
IPC分类号： G06F1100
CPC分类号： G06F13/4022
摘要： A method and system for packet-switched flow control of transaction requests that maximizes resource utilization and throughput, and minimizes latency. A system controller provides dedicated transaction request queues and controls the forwarding of transactions from a processor to a slave. The transaction requests are automatically forwarded to an intended slave on the same address bus as the system controller immediately. The system controller determines whether the proper criteria are met for that slave to receive such a request, such as the slave's request receive queue is not full and that global ordering requirements are met. If so, then on a separately provided line, the system controller validates the request for immediate reception by the slave.
摘要翻译：一种用于最大限度地提高资源利用率和吞吐量的事务请求的数据包交换流量控制的方法和系统，并使延迟最小化。系统控制器提供专用的事务请求队列并且控制事务从处理器到从属设备的转发。事务请求将立即自动转发到与系统控制器相同的地址总线上的预期从站。系统控制器确定是否满足该从站接收此类请求的适当标准，例如从站的请求接收队列不满并满足全局排序要求。如果是这样，则在单独提供的线路上，系统控制器验证从机立即接收的请求。

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