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1. 发明授权

US5444854A Input/output initiate command mechanism 失效
标题翻译：输入/输出启动命令机制
公开(公告)号：US5444854A
公开(公告)日：1995-08-22
申请号：US849643
申请日：1992-03-06
申请人： Joseph R. Mathis , Richard R. Oehler , Carl Zeitler, Jr.
发明人： Joseph R. Mathis , Richard R. Oehler , Carl Zeitler, Jr.
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/126
摘要： A data processing system including a processor that issues communications commands on a first communications channel and a peripheral device that is connected to the first communications channel and to a second communications channel that operates asynchronously relative to the first communications channel. The peripheral device performs communications operations specified from the commands from the processor and further responds to communications over the second communications channel. The peripheral device includes a controller that provides a status word to the processor in response to the command issued to the peripheral device. The status word indicates the status condition of the peripheral device at the time when the peripheral device initiates the operation specified by the issued command.
摘要翻译：一种数据处理系统，包括在第一通信信道上发布通信命令的处理器和连接到第一通信信道的外围设备以及相对于第一通信信道异步工作的第二通信信道。外围设备执行从处理器的命令指定的通信操作，并进一步响应通过第二通信信道的通信。外围设备包括响应于向外围设备发出的命令向处理器提供状态字的控制器。状态字表示外围设备启动由发出的命令指定的操作时的外围设备的状态。

2. 发明授权

US4995056A System and method for data communications 失效
标题翻译：用于数据通信的系统和方法
公开(公告)号：US4995056A
公开(公告)日：1991-02-19
申请号：US297776
申请日：1989-01-13
申请人： Richard G. Fogg, Jr. , Joseph R. Mathis , Carl Zeitler, Jr.
发明人： Richard G. Fogg, Jr. , Joseph R. Mathis , Carl Zeitler, Jr.
IPC分类号： H04L29/08 , G06F13/42
CPC分类号： G06F13/4213
摘要： In a communications system, a sending system and a receiving system have multiple data buffers. In response to an inquiry from the sending system, the receiving system transmits information which indicates the size and number of data buffers available in the receiving system. The sending system then begins transmitting data frames, which are placed into the buffers of the receiving system. When the receiving system removes all of the data from a buffer, therefore freeing it to accept additional data, it sends a signal to the sending system indicating this fact. The sending system counts such signals, and ensures that the number of transmitted data frames does not exceed the number of frames which have been removed from the receiver's buffers by more than the number of buffers which the receiver has.

3. 发明授权

US4455605A Method for establishing variable path group associations and affiliations between "non-static" MP systems and shared devices 失效
标题翻译：在“非静态”MP系统和共享设备之间建立可变路径组关联和关联的方法
公开(公告)号：US4455605A
公开(公告)日：1984-06-19
申请号：US286396
申请日：1981-07-23
申请人： Roger L. Cormier , Robert J. Dugan , Richard R. Guyette , Paul J. Wanish , Carl Zeitler, Jr.
发明人： Roger L. Cormier , Robert J. Dugan , Richard R. Guyette , Paul J. Wanish , Carl Zeitler, Jr.
IPC分类号： G06F13/12 , G06F13/14 , G06F13/40 , G06F15/177 , H04L29/00 , H04L29/04 , G06F3/04 , G06F13/00
CPC分类号： G06F13/4022 , G06F15/177
摘要： Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Related path state indications are stored peripherally in path map tables and define path group associations for sustaining path-independent I/O operations. When a device is reserved via one path in a path group the reserve affiliation is extended automatically (in the path tables ) to each path in the group, thereby rendering each path accessible in a reserved mode. The path defining commands are used for adding paths to, resigning paths from and disbanding groups. Special sensing commands are used for sensing path reservation and grouping states. When a command for adding or resigning a path is presented to a reserved device via one path in a group the reserve is automatically realigned to the enlarged or reduced group. When a command for disbanding a group is presented to a reserved device the reserve is realigned to apply only to the path on which the command is presented. The foregoing special commands are required to be obeyed by the device even if it currently has a conflicting allegiance to the same system or another system. Consequently, paths can be added to an established path group without requiring potentially premature release of any allegiance.
摘要翻译：具有可更改CPU配置的多处理系统可生成唯一可更改的标识（ID）。这些通过各种I / O连接路径的I / O通道与特殊路径定义命令和功能数据相关联。相关路径状态指示外围存储在路径映射表中，并定义用于维持与路径无关的I / O操作的路径组关联。当通过路径组中的一个路径保留设备时，保留联盟将自动扩展（在路径表中）到组中的每个路径，从而使每个路径在保留模式下可访问。路径定义命令用于添加路径，撤销和解散组的路径。特殊传感命令用于感测路径预留和分组状态。当通过组中的一个路径将添加或重新命名路径的命令呈现给保留设备时，保留将自动重新对准放大或缩小的组。当将分组解除组的命令呈现给保留设备时，保留被重新对齐以仅应用于显示命令的路径。上述特殊命令需要被设备遵守，即使它当前对相同的系统或其他系统具有冲突的效忠。因此，可以将路径添加到已建立的路径组中，而不需要潜在地过早释放任何效忠。

4. 发明授权

US4445176A Block transfers of information in data processing networks 失效
标题翻译：阻止数据处理网络中的信息传输
公开(公告)号：US4445176A
公开(公告)日：1984-04-24
申请号：US107806
申请日：1979-12-28
申请人： John L. Burk , Roger L. Cormier , Michael H. Hartung , Ray A. Larner , Donald J. Lucas , Kenneth R. Lynch , Brian B. Moore , Howard L. Page , David H. Wansor , Carl Zeitler, Jr.
发明人： John L. Burk , Roger L. Cormier , Michael H. Hartung , Ray A. Larner , Donald J. Lucas , Kenneth R. Lynch , Brian B. Moore , Howard L. Page , David H. Wansor , Carl Zeitler, Jr.
IPC分类号： G06F13/00 , G06F13/12 , G06F15/167
CPC分类号： G06F15/167 , G06F13/122
摘要： Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request. An "adapter" processor associated with each host and subsystem operates on an asynchronous basis to transfer messages and data relative to the associated host or subsystem. One or more processing "engines" in each adapter communicates with one or more CPU's in the associated host or subsystem through an associated "adapter store". A portion of each adapter store is used as a buffer pool for constructing "subchannel control spaces" to control transers of messages and data. Elements of each subchannel control space are returned to free status as soon as they are not needed for sustaining associated transfers.
摘要翻译：辅助存储子系统与主机数据处理系统交换消息和数据，并在主机系统之间转发消息。因此，主机系统除了能够访问子系统存储器中的数据之外还相互通信。通过从主机发送到子系统的“请求”启动对子系统存储的访问。每个请求是包含一个或多个命令的数组的消息，每个命令指定要由子系统执行的数据传送或控制功能。子系统可以一次处理多个请求。它还可以以适合于子系统资源的可用性和到主机系统的数据链路的任意顺序处理请求中的命令。在处理请求中的所有命令之后，子系统向发起请求的主机系统发送关联的“完成”消息。完成消息指示相关请求中的每个命令的完成状态或异常终止。与每个主机和子系统相关联的“适配器”处理器在异步的基础上操作以相对于相关联的主机或子系统传送消息和数据。每个适配器中的一个或多个处理“引擎”通过相关联的“适配器存储”与相关主机或子系统中的一个或多个CPU进行通信。每个适配器存储的一部分用作缓冲池，用于构建“子信道控制空间”来控制消息和数据的传输。每个子通道控制空间的元素一旦不需要维持相关的传输就返回到空闲状态。

5. 发明授权

US4271468A Multiprocessor mechanism for handling channel interrupts 失效
公开(公告)号：US4271468A
公开(公告)日：1981-06-02
申请号：US91902
申请日：1979-11-06
申请人： Neal T. Christensen , William C. Van Loo , Robert H. Werner , Joseph A. Wetzel , Carl Zeitler, Jr.
发明人： Neal T. Christensen , William C. Van Loo , Robert H. Werner , Joseph A. Wetzel , Carl Zeitler, Jr.
IPC分类号： G06F13/14 , G06F9/46 , G06F9/48 , G06F13/26 , G06F15/16 , G06F15/177 , G06F15/00
CPC分类号： G06F13/26
摘要： The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program.An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty.A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs.In each CP, acceptance determining circuits connect to the broadcast bus and accept the highest-priority-unmask non-empty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state.Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queue at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP.An inhibit register in the interrupt controller in the SC inhibits selected bits on the broadcast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends its acceptance of the corresponding queue, so that any CP can select the next entry on the corresponding queue.When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state.

6. 发明授权

US4497022A Method and apparatus for measurements of channel operation 失效
标题翻译：用于测量通道操作的方法和装置
公开(公告)号：US4497022A
公开(公告)日：1985-01-29
申请号：US435192
申请日：1982-10-19
申请人： Roger L. Cormier , Robert J. Dugan , Richard R. Guyette , Ronald L. Hankison , Ming C. Hao , Arthur L. Levin , George A. McClain , Paul J. Wanish , Carl Zeitler, Jr.
发明人： Roger L. Cormier , Robert J. Dugan , Richard R. Guyette , Ronald L. Hankison , Ming C. Hao , Arthur L. Levin , George A. McClain , Paul J. Wanish , Carl Zeitler, Jr.
IPC分类号： G06F11/34 , G06F3/00
CPC分类号： G06F11/3419 , G06F11/3423 , G06F11/349 , G06F2201/86 , G06F2201/88
摘要： A channel for a data processing system is provided with a time of day clock that is synchronized with the time of day clock of the associated central processor. Both the central processor and the channel processor record times of particular events, and the channel uses these times to calculate two times called Function Pending and Function Active. Both times begin when the central processor executes an instruction to begin an I/O operation. Function Pending ends when the channel has made successful initial selection. This time shows delays by the channel processor in scheduling the channel control unit, and device resources for I/O operations. Function Active ends at Channel End. A new instruction, Set Channel Monitor, enables or disables these measurements. An information block for each subchannel defines one of several measurement modes for a subchannel or disables the subchannel from measurement.
摘要翻译：数据处理系统的通道具有与相关联的中央处理器的时钟同步的时钟。中央处理器和通道处理器记录特定事件的时间，通道使用这些时间来计算两次称为功能待处理和功能活动。当中央处理器执行开始I / O操作的指令时，两者都开始。功能当通道成功初始选择时，挂起结束。这个时间表示信道处理器在调度信道控制单元时的延迟，以及用于I / O操作的设备资源。功能在通道结束处有效。设置通道监视器的新指令启用或禁用这些测量。每个子信道的信息块定义子信道的几种测量模式之一或禁止子信道进行测量。

7. 发明授权

US06986069B2 Methods and apparatus for static and dynamic power management of computer systems 失效
标题翻译：计算机系统静态和动态电源管理的方法和装置
公开(公告)号：US06986069B2
公开(公告)日：2006-01-10
申请号：US10188271
申请日：2002-07-01
申请人： Richard R. Oehler , Carl Zeitler, Jr. , Richard O. Simpson
发明人： Richard R. Oehler , Carl Zeitler, Jr. , Richard O. Simpson
IPC分类号： G06F1/32 , G06F1/28 , G06F1/26
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/329 , Y02D10/171 , Y02D10/24
摘要： According to the present invention, methods and apparatus are provided for static and dynamic power management of computer systems. A power authority manages power usage levels in computer systems by monitoring power consumption levels and providing power consumption information to the various systems. In one example, the power authority updates power tables to vary aggregate power consumption levels.
摘要翻译：根据本发明，提供了用于计算机系统的静态和动态功率管理的方法和装置。电力机构通过监测电力消耗水平并向各种系统提供功耗信息来管理计算机系统中的电力使用水平。在一个示例中，电源机构更新功率表以改变总体功耗级别。

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