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    • 1. 发明授权
    • Input/output initiate command mechanism
    • 输入/输出启动命令机制
    • US5444854A
    • 1995-08-22
    • US849643
    • 1992-03-06
    • Joseph R. MathisRichard R. OehlerCarl Zeitler, Jr.
    • Joseph R. MathisRichard R. OehlerCarl Zeitler, Jr.
    • G06F13/12G06F13/00
    • G06F13/126
    • A data processing system including a processor that issues communications commands on a first communications channel and a peripheral device that is connected to the first communications channel and to a second communications channel that operates asynchronously relative to the first communications channel. The peripheral device performs communications operations specified from the commands from the processor and further responds to communications over the second communications channel. The peripheral device includes a controller that provides a status word to the processor in response to the command issued to the peripheral device. The status word indicates the status condition of the peripheral device at the time when the peripheral device initiates the operation specified by the issued command.
    • 一种数据处理系统,包括在第一通信信道上发布通信命令的处理器和连接到第一通信信道的外围设备以及相对于第一通信信道异步工作的第二通信信道。 外围设备执行从处理器的命令指定的通信操作,并进一步响应通过第二通信信道的通信。 外围设备包括响应于向外围设备发出的命令向处理器提供状态字的控制器。 状态字表示外围设备启动由发出的命令指定的操作时的外围设备的状态。
    • 3. 发明授权
    • Method for establishing variable path group associations and
affiliations between
    • 在“非静态”MP系统和共享设备之间建立可变路径组关联和关联的方法
    • US4455605A
    • 1984-06-19
    • US286396
    • 1981-07-23
    • Roger L. CormierRobert J. DuganRichard R. GuyettePaul J. WanishCarl Zeitler, Jr.
    • Roger L. CormierRobert J. DuganRichard R. GuyettePaul J. WanishCarl Zeitler, Jr.
    • G06F13/12G06F13/14G06F13/40G06F15/177H04L29/00H04L29/04G06F3/04G06F13/00
    • G06F13/4022G06F15/177
    • Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Related path state indications are stored peripherally in path map tables and define path group associations for sustaining path-independent I/O operations. When a device is reserved via one path in a path group the reserve affiliation is extended automatically (in the path tables ) to each path in the group, thereby rendering each path accessible in a reserved mode. The path defining commands are used for adding paths to, resigning paths from and disbanding groups. Special sensing commands are used for sensing path reservation and grouping states. When a command for adding or resigning a path is presented to a reserved device via one path in a group the reserve is automatically realigned to the enlarged or reduced group. When a command for disbanding a group is presented to a reserved device the reserve is realigned to apply only to the path on which the command is presented. The foregoing special commands are required to be obeyed by the device even if it currently has a conflicting allegiance to the same system or another system. Consequently, paths can be added to an established path group without requiring potentially premature release of any allegiance.
    • 具有可更改CPU配置的多处理系统可生成唯一可更改的标识(ID)。 这些通过各种I / O连接路径的I / O通道与特殊路径定义命令和功能数据相关联。 相关路径状态指示外围存储在路径映射表中,并定义用于维持与路径无关的I / O操作的路径组关联。 当通过路径组中的一个路径保留设备时,保留联盟将自动扩展(在路径表中)到组中的每个路径,从而使每个路径在保留模式下可访问。 路径定义命令用于添加路径,撤销和解散组的路径。 特殊传感命令用于感测路径预留和分组状态。 当通过组中的一个路径将添加或重新命名路径的命令呈现给保留设备时,保留将自动重新对准放大或缩小的组。 当将分组解除组的命令呈现给保留设备时,保留被重新对齐以仅应用于显示命令的路径。 上述特殊命令需要被设备遵守,即使它当前对相同的系统或其他系统具有冲突的效忠。 因此,可以将路径添加到已建立的路径组中,而不需要潜在地过早释放任何效忠。
    • 4. 发明授权
    • Block transfers of information in data processing networks
    • 阻止数据处理网络中的信息传输
    • US4445176A
    • 1984-04-24
    • US107806
    • 1979-12-28
    • John L. BurkRoger L. CormierMichael H. HartungRay A. LarnerDonald J. LucasKenneth R. LynchBrian B. MooreHoward L. PageDavid H. WansorCarl Zeitler, Jr.
    • John L. BurkRoger L. CormierMichael H. HartungRay A. LarnerDonald J. LucasKenneth R. LynchBrian B. MooreHoward L. PageDavid H. WansorCarl Zeitler, Jr.
    • G06F13/00G06F13/12G06F15/167
    • G06F15/167G06F13/122
    • Secondary storage subsystems exchange messages and data with host data processing systems and also forward messages between host systems. Host systems thereby communicate with each other in addition to having access to data in subsystem storage. Access to subsystem storage is initiated by a "request" sent from a host to the subsystem. Each request is a message containing an array of one or more commands, each command specifying a transfer of data or a control function to be performed by the subsystem. A subsystem may process more than one request at a time. It also may process the commands in a request in an arbitrary sequence suited to the availability of subsystem resources and data links to host systems. After all commands in a request have been processed the subsystem transmits an associated "completion" message to the host system which originated the request. The completion message indicates the status of completion or abnormal termination of each command in the associated request. An "adapter" processor associated with each host and subsystem operates on an asynchronous basis to transfer messages and data relative to the associated host or subsystem. One or more processing "engines" in each adapter communicates with one or more CPU's in the associated host or subsystem through an associated "adapter store". A portion of each adapter store is used as a buffer pool for constructing "subchannel control spaces" to control transers of messages and data. Elements of each subchannel control space are returned to free status as soon as they are not needed for sustaining associated transfers.
    • 辅助存储子系统与主机数据处理系统交换消息和数据,并在主机系统之间转发消息。 因此,主机系统除了能够访问子系统存储器中的数据之外还相互通信。 通过从主机发送到子系统的“请求”启动对子系统存储的访问。 每个请求是包含一个或多个命令的数组的消息,每个命令指定要由子系统执行的数据传送或控制功能。 子系统可以一次处理多个请求。 它还可以以适合于子系统资源的可用性和到主机系统的数据链路的任意顺序处理请求中的命令。 在处理请求中的所有命令之后,子系统向发起请求的主机系统发送关联的“完成”消息。 完成消息指示相关请求中的每个命令的完成状态或异常终止。 与每个主机和子系统相关联的“适配器”处理器在异步的基础上操作以相对于相关联的主机或子系统传送消息和数据。 每个适配器中的一个或多个处理“引擎”通过相关联的“适配器存储”与相关主机或子系统中的一个或多个CPU进行通信。 每个适配器存储的一部分用作缓冲池,用于构建“子信道控制空间”来控制消息和数据的传输。 每个子通道控制空间的元素一旦不需要维持相关的传输就返回到空闲状态。
    • 5. 发明授权
    • Multiprocessor mechanism for handling channel interrupts
    • US4271468A
    • 1981-06-02
    • US91902
    • 1979-11-06
    • Neal T. ChristensenWilliam C. Van LooRobert H. WernerJoseph A. WetzelCarl Zeitler, Jr.
    • Neal T. ChristensenWilliam C. Van LooRobert H. WernerJoseph A. WetzelCarl Zeitler, Jr.
    • G06F13/14G06F9/46G06F9/48G06F13/26G06F15/16G06F15/177G06F15/00
    • G06F13/26
    • The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program.An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty.A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs.In each CP, acceptance determining circuits connect to the broadcast bus and accept the highest-priority-unmask non-empty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state.Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queue at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP.An inhibit register in the interrupt controller in the SC inhibits selected bits on the broadcast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends its acceptance of the corresponding queue, so that any CP can select the next entry on the corresponding queue.When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state.