会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明授权
    • Parallelized coherent read and writeback transaction processing system
for use in a packet switched cache coherent multiprocessor system
    • 并行相干读写事务处理系统,用于分组交换高速缓存一致多处理器系统
    • US5581729A
    • 1996-12-03
    • US414763
    • 1995-03-31
    • Satyanarayana NishtalaZahir EbrahimWilliam C. Van LooPaul LoewensteinSue K. LeeLouis F. Coffin III
    • Satyanarayana NishtalaZahir EbrahimWilliam C. Van LooPaul LoewensteinSue K. LeeLouis F. Coffin III
    • G06F12/08G06F13/00
    • G06F12/0828G06F12/0822
    • A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.
    • 提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。 互连模块根据从系统控制器接收的互连控制信号,互连主存储器和子系统。 至少两个子系统是数据处理器,每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。 每个主缓存索引具有一组主缓存标签(Etags),包括缓存存储器存储的每个数据块的一个缓存标签。 每个数据处理器包括具有用于向系统控制器发送存储器事务请求的主类的主接口。 系统控制器包括用于由数据处理器处理每个存储器事务请求的存储器事务请求逻辑。 系统控制器维护具有每个数据处理器的一组重复缓存标签(Dtags)的重复缓存索引。 每个数据处理器具有用于存储先前存储在受害高速缓存行中的数据块的回写缓冲器,直到其各自的回写事务完成为止,以及用于存储与先前执行的读取事务相关联的高速缓存行的高速缓存状态的第N + 1个Dtag 到读写回事务对的相关回写事务。 因此,在高速缓存未命中时,互连可以依赖于回写缓冲器或Nth + 1Dtag并行地执行读取和回写事务,以适应事务的任何排序。