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1. 发明授权

US5987579A Method and apparatus for quickly initiating memory accesses in a multiprocessor cache coherent computer system 失效
标题翻译：用于在多处理器高速缓存一致计算机系统中快速启动存储器访问的方法和装置
公开(公告)号：US5987579A
公开(公告)日：1999-11-16
申请号：US825404
申请日：1997-03-27
申请人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Raymond Ng , Louis F. Coffin, III
发明人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Raymond Ng , Louis F. Coffin, III
IPC分类号： G06F13/16 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0884
摘要： In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.
摘要翻译：在包括分组交换总线的计算机系统中，用于请求事务的方法使得快速启动存储器访问。主设备发送具有多个部分的事务请求分组的第一部分。存储器控制器接收事务请求的第一部分，其包括存储器地址的行地址部分。响应于接收到请求分组的第一部分，存储器控制器通过将行地址选通信号施加到存储器位置的行来启动存储器访问，并且主机传输事务请求的任何剩余部分。在接收到完整存储器地址之后，确定存储在存储器位置的数据是否要从存储器位置以外的源读取。如果要从除存储器位置之外的源读取数据，则存储器控制器通过禁止对存储器位置的列存取选通信号的断言来中止存储器访问。

2. 发明授权

US5905998A Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system 失效
标题翻译：用于控制分组交换高速缓存一致多处理器系统中的存储器事务处理的事务激活处理器
公开(公告)号：US5905998A
公开(公告)日：1999-05-18
申请号：US858792
申请日：1997-05-19
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.
摘要翻译：多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。一些子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器以及相应的主缓存标签集（Etag），包括由高速缓冲存储器存储的每个数据块的一个Etag。每个数据处理器包括一个接口，用于向系统控制器发送存储器事务请求，并接收来自系统控制器的高速缓存事务请求，对应于其他数据处理器的存储器事务请求。系统控制器包括事务激活逻辑，用于当其满足预定义的激活准则时激活每个所述存储器事务请求，并且用于阻止每个所述存储器事务请求直到满足预定义的激活标准。活动事务状态表存储表示已激活的存储器事务请求的状态数据，包括每个激活的事务的地址值。事务激活逻辑包括比较器逻辑，用于将每个存储器事务请求与所有激活的存储器事务请求的活动事务状态数据进行比较，以便检测特定存储器事务请求的激活是否违反预定义的激活标准。对于回写事务有一些例外，用于访问映射到相同高速缓存行的未决事务，先前激活的事务的数据块的传入事务将被阻止，直到映射到同一高速缓存行的挂起事务完成。

3. 发明授权

US5862356A Pipelined distributed bus arbitration system 失效
标题翻译：流水线分布式总线仲裁系统
公开(公告)号：US5862356A
公开(公告)日：1999-01-19
申请号：US870438
申请日：1997-06-04
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
IPC分类号： G06F15/16 , G06F13/368 , G06F13/374 , G06F15/177 , G06F13/00
CPC分类号： G06F13/368 , G06F13/374
摘要： The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration occurs within all the respective bus arbiters occurs in a second clock cycle.
摘要翻译：本发明提供了一种可扩展的，模块化和流水线分布式总线仲裁系统，用于有效地分辨耦合到公共系统总线的子系统（例如处理器）之间的总线争用。仲裁系统包括多个分布式总线仲裁器，其接收来自子系统的总线请求并独立地确定下一个总线主机。仲裁协议使仲裁过程能够从临界定时路径中消除，从而允许系统以给定的集成电路（IC）技术可能的最大系统时钟频率工作，以减少整体系统时钟延迟。在仲裁时钟周期期间，子系统之间的任何改变都是基于任何在仲裁时钟周期之前的时钟周期期间有效的系统总线请求，并且独立于在系统总线请求期间断言的任何系统总线请求仲裁时钟周期。此外，仲裁协议优先处理当前总线主机，即总线主机驱动系统总线。无论处理器速度如何，每个仲裁任务都在系统时钟周期内完成。因此，用于保留当前总线主机的仲裁延迟是一个系统时钟周期，而用于选择和切换总线主机的延迟是两个系统时钟周期。在此实现中，最后一个端口驱动程序是允许在时钟周期内断言总线请求的唯一子系统，并在下一个即时时钟周期内立即驱动系统总线。相反，当不是最后端口驱动器的第二子系统需要驱动非活动系统总线时，第二子系统在第一时钟周期内断言其总线请求线，并且在所有相应的总线仲裁器内进行仲裁发生在第二个时钟周期。

4. 发明授权

US06381664B1 System for multisized bus coupling in a packet-switched computer system 有权
标题翻译：在分组交换计算机系统中用于多尺寸总线耦合的系统
公开(公告)号：US06381664B1
公开(公告)日：2002-04-30
申请号：US09597963
申请日：2000-06-20
申请人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
发明人： Satyanarayana Nishtala , William C. Van Loo , Zahir Ebrahim
IPC分类号： G06F1300
CPC分类号： G06F13/4018
摘要： A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.
摘要翻译：一种用于具有分组交换数据总线的计算机系统的数据传输控制系统，用于控制从具有一个总线宽度的设备到具有不同总线宽度的设备的数据字的传送。第一总线可以是主总线，第二总线是连接到计算机系统并耦合到主总线的诸如存储器或其他设备的功能单元的总线。当第二总线小于第一总线时，数据传输控制系统通过仅将每个时钟周期的部分字传送到第二总线来适应这种情况，有效延迟数据传输到第二总线可以处理的速率。传输速率因子基本上等于第二总线宽度与第一总线宽度的比率。在替代实施例中，数据传输控制系统以给定计算机系统的处理器或时钟速度和主总线的宽度的基本上可利用的全速率传送数据字，并且在传送到第二总线之前缓冲字。然后，传输到缓冲器的速度不受第二总线的大小限制，而仅由缓冲器的大小限制，缓冲器的大小优选地具有至少与母线总线相同的输入总线。该系统可容纳不同尺寸的功能单元，以连接到给定尺寸的主总线，其中不同尺寸可能大于或小于主总线尺寸，因此功能单元可以以最佳总线大小来构建特定功能，而不必符合可能不合适，低效或昂贵或浪费的主总线大小。

5. 发明授权

US5684977A Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system 失效
标题翻译：回写取消处理系统，用于分组交换高速缓存一致多处理器系统
公开(公告)号：US5684977A
公开(公告)日：1997-11-04
申请号：US415040
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect. The transaction execution circuitry pipelines memory access requests from the data processors, and includes invalidation circuitry for processing each writeback request from a given data processor prior to activation to determine if the Dtag index corresponding to the victimized cache line is invalid. Thereafter, the invalidation circuitry activates writeback requests only if the Dtag index is not invalid and cancels the writeback request if the Dtag index is invalid.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应缓存存储器和一组主缓存标签（Etags），包括由高速缓存存储器存储的每个数据块的一个高速缓存标签。每个数据处理器包括用于向系统控制器发送存储器事务请求的主接口。系统控制器处理每个存储器事务，并为每个数据处理器维护一组重复的缓存标签（Dtags）。最后，系统控制器包含用于激活交易以进行互连维修的事务执行电路。交易执行电路管理来自数据处理器的存储器访问请求，并且包括用于在激活之前处理来自给定数据处理器的每个回写请求的无效电路，以确定与受害高速缓存行对应的Dtag索引是否无效。此后，无效电路仅在Dtag索引无效时才激活写回请求，如果Dtag索引无效则取消写回请求。

6. 发明授权

US5644753A Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system 失效
标题翻译：快速，双端口缓存控制器，用于数据包交换缓存一致多处理器系统中的数据处理器
公开(公告)号：US5644753A
公开(公告)日：1997-07-01
申请号：US714965
申请日：1996-09-17
申请人： Zahir Ebrahim , Kevin Normoyle , Satyanarayana Nishtala , William C. Van Loo
发明人： Zahir Ebrahim , Kevin Normoyle , Satyanarayana Nishtala , William C. Van Loo
IPC分类号： G11C11/41 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0833
摘要： A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data processor and a second port receives access requests from the system controller. All cache memory access requests include an address value; access requests from the system controller also include a mode flag. A comparator in the cache controller processes the address value in each access request and generates a hit/miss signal indicating whether the data block corresponding to the address value is stored in the cache memory. The cache controller has two modes of operation, including a first standard mode of operation in which read/write access to the cache memory is preceded by generation of the hit/miss signal by the comparator, and a second accelerated mode of operation in which read/write access to the cache memory is initiated without waiting for the comparator to process the access request's address value. The first mode of operation is used for all access requests by the data processor and for system controller access requests when the mode flag has a first value. The second mode of operation is used for the system controller access requests when the mode flag has a second value distinct from the first value.
摘要翻译：多处理器计算机系统具有耦合到系统控制器的数据处理器和主存储器。每个数据处理器都有一个缓存存储器。每个高速缓冲存储器具有一个具有两个用于接收访问请求的端口的缓存控制器。第一端口从相关联的数据处理器接收访问请求，第二端口从系统控制器接收访问请求。所有高速缓存存储器访问请求都包含一个地址值; 来自系统控制器的访问请求还包括模式标志。高速缓存控制器中的比较器处理每个访问请求中的地址值，并产生指示与地址值相对应的数据块是否存储在高速缓冲存储器中的命中/未命中信号。高速缓存控制器具有两种操作模式，包括第一标准操作模式，其中先前通过比较器生成命中/未命中信号，其中对高速缓冲存储器的读/写访问以及其中读取的第二加速操作模式启动对高速缓冲存储器的写入访问，而不必等待比较器处理访问请求的地址值。当模式标志具有第一个值时，第一种操作模式用于数据处理器和系统控制器访问请求的所有访问请求。当模式标志具有与第一值不同的第二值时，第二操作模式用于系统控制器访问请求。

7. 发明授权

US5692197A Method and apparatus for reducing power consumption in a computer network without sacrificing performance 失效
标题翻译：用于在不牺牲性能的情况下降低计算机网络中的功耗的方法和装置
公开(公告)号：US5692197A
公开(公告)日：1997-11-25
申请号：US414879
申请日：1995-03-31
申请人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
发明人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
IPC分类号： G06F1/32 , G06F15/16 , G06F15/177
CPC分类号： G06F1/3209
摘要： A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups. Conversely, the source of asynchronous events are external in nature and include input/output (I/O) activity. The illusion of the entire network being always fully operational is possible because the system controllers, the interconnects and network interfaces of each computer system remain fully operational while selected modules and peripheral devices are powered down. As a result, each computer system is able to rapidly awake from sleep state in response to stimuli by powering down selected modules thereby accomplishing power conservation without requiring a static shut down of the computer network, i.e., without the overall performance and response of the computer network.
摘要翻译：一种用于主动管理计算机网络的整体功耗的方法和装置，其包括彼此互连的多个计算机系统。反过来，每个计算机系统具有一个或多个模块。计算机网络的每个计算机系统能够独立地启动向省电模式转变，即“休眠”状态，同时保持其网络接口“活着”并且完全可操作。随后，当由确定性或异步事件触发时，每个计算机系统可以独立地转换回完全操作状态，即“清醒”状态。因此，计算机系统的睡眠状态对于计算机网络是透明的。确定性事件是由计算机系统在内部触发的事件，例如内部定时器在午夜唤醒计算机系统以执行诸如日常磁带备份的家务杂务。相反，异步事件的来源本质上是外部的，包括输入/输出（I / O）活动。整个网络的错觉始终是完全可操作的，因为每个计算机系统的系统控制器，互连和网络接口在选定的模块和外围设备关闭电源时保持完全可操作。因此，每个计算机系统能够通过断电所选择的模块来迅速地从睡眠状态唤醒，从而实现功率节省，而不需要静态关闭计算机网络，即没有计算机的整体性能和响应网络。

8. 发明授权

US5634068A Packet switched cache coherent multiprocessor system 失效
标题翻译：分组交换缓存一致多处理器系统
公开(公告)号：US5634068A
公开(公告)日：1997-05-27
申请号：US415175
申请日：1995-03-31
申请人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0822
摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems include a port that transmits and receives data as data packets of a fixed size. At least two of the sub-systems are data processors, each having a respective cache memory and a respective set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. The system controller maintains a set of duplicate cache tags (Dtags) for each of the data processors. The data processors each include master cache logic for updating the master cache tags, while the system controller includes logic for updating the duplicate cache tags. Memory transaction request logic simultaneously looks up the second cache tag in each of the sets of duplicate cache tags corresponding to the memory transaction request. It then determines which one of the cache memories and main memory to couple to the requesting data processor based on the second cache states and the address tags stored in the corresponding second cache tags. Duplicate cache update logic simultaneously updates all of the corresponding second cache tags in accordance with predefined cache tag update criteria.
摘要翻译：多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。所有子系统都包括一个端口，该端口作为固定大小的数据包发送和接收数据。至少两个子系统是数据处理器，每个数据处理器具有相应的高速缓冲存储器和相应的主缓存标签集（Etags），包括由高速缓存存储器存储的每个数据块的一个高速缓存标签。系统控制器为每个数据处理器维护一组重复的缓存标签（Dtags）。数据处理器各自包括用于更新主缓存标签的主缓存逻辑，而系统控制器包括用于更新重复高速缓存标签的逻辑。存储器事务请求逻辑同时查找对应于存储器事务请求的每组重复高速缓存标签中的第二高速缓存标签。然后，基于存储在相应的第二高速缓存标签中的第二高速缓存状态和地址标签，确定哪个高速缓冲存储器和主存储器耦合到请求数据处理器。重复的高速缓存更新逻辑根据预定义的缓存标签更新标准同时更新所有相应的第二高速缓存标签。

9. 发明授权

US5907485A Method and apparatus for flow control in packet-switched computer system 失效
标题翻译：分组交换计算机系统中流控制的方法和装置
公开(公告)号：US5907485A
公开(公告)日：1999-05-25
申请号：US414875
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F9/46 , G06F13/24 , G05B15/00
CPC分类号： G06F9/546 , G06F13/24
摘要： This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.
摘要翻译：本发明描述了一种用于分组交换单处理器和多处理器计算机系统的链路链路流控制方法，其使系统资源利用率和吞吐量最大化，并最小化系统等待时间。计算机系统包括一个或多个主接口，一个或多个从接口和互连系统控制器，其为每个主接口提供专用事务请求队列，并且控制事务到每个从接口的转发。主接口跟踪系统控制器中专用队列中的请求数，系统控制器跟踪每个从接口队列中的请求数。主接口和系统控制器都知道其下游队列的最大容量，并且不会比下游队列可以容纳更多的事务请求。来自下游队列的确认向发送方指示在其中存在另一个事务的空间。因此，尝试将请求发送到已满的队列时，不会浪费任何系统资源。

10. 发明授权

US5655100A Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system 失效
标题翻译：用于控制分组交换高速缓存一致多处理器系统中的存储器事务执行的事务激活处理器
公开(公告)号：US5655100A
公开(公告)日：1997-08-05
申请号：US414772
申请日：1995-03-31
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.
摘要翻译：多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。一些子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器以及相应的主缓存标签集（Etag），包括由高速缓冲存储器存储的每个数据块的一个Etag。每个数据处理器包括一个接口，用于向系统控制器发送存储器事务请求，并接收来自系统控制器的高速缓存事务请求，对应于其他数据处理器的存储器事务请求。系统控制器包括事务激活逻辑，用于当其满足预定义的激活准则时激活每个所述存储器事务请求，并且用于阻止每个所述存储器事务请求直到满足预定义的激活标准。活动事务状态表存储表示已激活的存储器事务请求的状态数据，包括每个激活的事务的地址值。事务激活逻辑包括比较器逻辑，用于将每个存储器事务请求与所有激活的存储器事务请求的活动事务状态数据进行比较，以便检测特定存储器事务请求的激活是否违反预定义的激活标准。对于回写事务有一些例外，用于访问映射到相同高速缓存行的未决事务，先前激活的事务的数据块的传入事务将被阻止，直到映射到同一高速缓存行的挂起事务完成。

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