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1. 发明授权

US5892957A Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system 失效
标题翻译：用于基于分组交换微处理器的计算机系统中的中断通信的方法和装置
公开(公告)号：US5892957A
公开(公告)日：1999-04-06
申请号：US868171
申请日：1997-06-03
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

2. 发明授权

US5689713A Method and apparatus for interrupt communication in a packet-switched computer system 失效
标题翻译：分组交换计算机系统中的中断通信的方法和装置
公开(公告)号：US5689713A
公开(公告)日：1997-11-18
申请号：US425537
申请日：1995-04-20
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

3. 发明授权

US5692197A Method and apparatus for reducing power consumption in a computer network without sacrificing performance 失效
标题翻译：用于在不牺牲性能的情况下降低计算机网络中的功耗的方法和装置
公开(公告)号：US5692197A
公开(公告)日：1997-11-25
申请号：US414879
申请日：1995-03-31
申请人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
发明人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
IPC分类号： G06F1/32 , G06F15/16 , G06F15/177
CPC分类号： G06F1/3209
摘要： A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups. Conversely, the source of asynchronous events are external in nature and include input/output (I/O) activity. The illusion of the entire network being always fully operational is possible because the system controllers, the interconnects and network interfaces of each computer system remain fully operational while selected modules and peripheral devices are powered down. As a result, each computer system is able to rapidly awake from sleep state in response to stimuli by powering down selected modules thereby accomplishing power conservation without requiring a static shut down of the computer network, i.e., without the overall performance and response of the computer network.
摘要翻译：一种用于主动管理计算机网络的整体功耗的方法和装置，其包括彼此互连的多个计算机系统。反过来，每个计算机系统具有一个或多个模块。计算机网络的每个计算机系统能够独立地启动向省电模式转变，即“休眠”状态，同时保持其网络接口“活着”并且完全可操作。随后，当由确定性或异步事件触发时，每个计算机系统可以独立地转换回完全操作状态，即“清醒”状态。因此，计算机系统的睡眠状态对于计算机网络是透明的。确定性事件是由计算机系统在内部触发的事件，例如内部定时器在午夜唤醒计算机系统以执行诸如日常磁带备份的家务杂务。相反，异步事件的来源本质上是外部的，包括输入/输出（I / O）活动。整个网络的错觉始终是完全可操作的，因为每个计算机系统的系统控制器，互连和网络接口在选定的模块和外围设备关闭电源时保持完全可操作。因此，每个计算机系统能够通过断电所选择的模块来迅速地从睡眠状态唤醒，从而实现功率节省，而不需要静态关闭计算机网络，即没有计算机的整体性能和响应网络。

4. 发明授权

US5657472A Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor 失效
标题翻译：具有与每个处理器相关联的独立并行事务队列的多处理器系统的内存事务执行系统和方法
公开(公告)号：US5657472A
公开(公告)日：1997-08-12
申请号：US414922
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III , Charles E. Narad
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Leslie Kohn , Louis F. Coffin, III , Charles E. Narad
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0828
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for each master class, for transmitting and receiving memory access requests. The system controller further includes memory transaction request logic for processing each memory transaction request and a duplicate cache index having a set of duplicate cache tags (Dtags), including one cache tag corresponding to each master cache tag in an associated data processor.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。每个主缓存索引具有一组主缓存标签（Etags），包括缓存存储器存储的每个数据块的一个缓存标签。每个数据处理器包括主界面，用于向系统控制器发送存储器事务请求，以及从其他数据处理器接收来自系统控制器的对应于存储器事务请求的高速缓存访问请求。在优选实施例中，每个存储器事务请求被分类为两个不同的主类之一：包括读存储器访问请求的第一事务类和包括回写存储器访问请求的第二事务类。主接口和系统控制器具有对应的并行请求队列，每个主类一个，用于发送和接收存储器访问请求。系统控制器还包括用于处理每个存储器事务请求的存储器事务请求逻辑和具有一组重复高速缓存标签（Dtags）的重复高速缓存索引，包括与相关联的数据处理器中的每个主高速缓存标签相对应的一个高速缓存标签。

5. 发明授权

US5367695A Bus-to-bus interface for preventing data incoherence in a multiple processor computer system 失效
标题翻译：总线到总线接口，用于防止多处理器计算机系统中的数据不一致
公开(公告)号：US5367695A
公开(公告)日：1994-11-22
申请号：US766784
申请日：1991-09-27
申请人： Charles E. Narad , Sun-Den Chen
发明人： Charles E. Narad , Sun-Den Chen
IPC分类号： G06F15/167 , G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A bus-to-bus interface preserves data coherence between masters and slaves operating within a multiple processor computer system. Two buses are connected via the interface. The first bus connects a number of self-identifying masters. The second bus connects a number of master devices and a number of slave devices. The second bus has no mechanism with which devices connected to the second bus may identify themselves. The interface contains a pair of registers for each slave device connected through the second bus. One register stores a busy bit if the corresponding slave is engaged on behalf of a master. The second register stores an identifying code for the master delegating a task to the corresponding slave. When a slave has accepted a task on behalf of a master and commanded the master to relinquish the bus, the busy register will be set and the master identification register will store the identifying code for the delegating master. Thereafter no master will be permitted to access the engaged slave unless the master identification code is that of the delegating master. Moreover, a delegating master will be denied access to the slave by that slave until the slave has completed the task accepted on behalf of the master. By preventing unintended masters from accessing slaves prior to the delegating master, inadvertent data transferred to the wrong master is avoided. Data coherence between master and slave is thereby ensured.
摘要翻译：总线到总线接口保持在多处理器计算机系统中操作的主机和从机之间的数据一致性。通过接口连接两条总线。第一条公交车连接了一些自我识别的主人。第二总线连接多个主设备和多个从设备。第二总线没有与第二总线连接的设备可以识别自身的机制。该接口包含一对通过第二总线连接的从设备的寄存器。如果相应的从站代表主站，则一个寄存器存储忙位。第二个寄存器存储用于将任务委托给相应从站的主机的识别码。当一个从机代表一个主机接受一个任务，并命令主机放弃总线时，忙位寄存器将被置位，主机识别寄存器将存储授权主机的识别代码。此后，除非主机识别码是授权主机的主机识别码，否则不允许主机访问从机从机。此外，委托主人将被该从机拒绝访问从机，直到从机完成代表主机接受的任务。通过防止无意的主人在授权主人之前访问从属，避免了传送到错误的主机的无意的数据。从而确保了主机与从机之间的数据一致性。

6. 发明授权

US5727219A Virtual input/output processor utilizing an interrupt handler 失效
标题翻译：虚拟输入/输出处理器利用中断处理程序
公开(公告)号：US5727219A
公开(公告)日：1998-03-10
申请号：US854113
申请日：1997-05-09
申请人： Thomas L. Lyon , Sun-Den Chen , William Joy , Leslie D. Kohn , Charles E. Narad , Robert Yung
发明人： Thomas L. Lyon , Sun-Den Chen , William Joy , Leslie D. Kohn , Charles E. Narad , Robert Yung
IPC分类号： G06F13/10 , G06F13/28 , G06F13/38 , G06F9/46 , G06F13/24
CPC分类号： G06F13/28 , G06F13/10 , G06F13/385
摘要： A virtual I/O processor (VIOP) is implemented using a programmed I/O (PIO) unit. The PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures. Preferably, the PIO unit is further complemented with a set of dedicated I/O global registers, a number of VIOP library read/write routines for various I/O device types, and non-blocking read and write operations. During execution, these elements cooperate with each other to perform multiple sequences of programmed I/Os as if they were being performed by a dedicated I/O processor.
摘要翻译：使用编程的I / O（PIO）单元实现虚拟I / O处理器（VIOP）。 PIO单元由VIOP中断，VIOP中断处理程序和多个VIOP数据结构补充。优选地，PIO单元进一步补充有一组专用I / O全局寄存器，用于各种I / O设备类型的多个VIOP库读/写例程以及非阻塞读写操作。在执行期间，这些元件彼此协作以执行多个编程I / O序列，就像它们由专用I / O处理器执行一样。

7. 发明授权

US06401117B1 Platform permitting execution of multiple network infrastructure applications 失效
标题翻译：平台允许执行多个网络基础设施应用程序
公开(公告)号：US06401117B1
公开(公告)日：2002-06-04
申请号：US09282790
申请日：1999-03-31
申请人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
发明人： Charles E. Narad , Kevin Fall , Neil MacAvoy , Pradip Shankar , Leonard M. Rand , Jerry J. Hall
IPC分类号： G06F1300
CPC分类号： H04L45/16 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30127 , G06F9/30145 , G06F9/30167 , G06F9/3885 , H04L29/06 , H04L41/0893 , H04L47/10 , H04L47/627 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9047 , H04L49/9094 , H04L69/03 , H04L69/12
摘要： The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets, management of buffer flow, encryption services, and management of Network Interface Controllers are accelerated through the use of a multiplicity of specialized modules. A language interface is defined for specifying both stateless and stateful classification of packets and to associate actions with classification results in order to efficiently utilize these specialized modules.
摘要翻译：本发明涉及一种用于加速网络基础设施应用的通用可编程分组处理平台，其被构造为分离分类和动作的阶段。通过使用多种专用模块，可以加速网络数据包分类，对这些数据包的操作执行，缓冲流的管理，加密服务和网络接口控制器的管理。定义了一种语言界面，用于指定数据包的无状态和有状态分类，并将动作与分类结果相关联，以便有效地利用这些专用模块。

8. 发明授权

US5287503A System having control registers coupled to a bus whereby addresses on the bus select a control register and a function to be performed on the control register 失效
标题翻译：具有耦合到总线的控制寄存器的系统，总线上的地址选择控制寄存器和在控制寄存器上执行的功能
公开(公告)号：US5287503A
公开(公告)日：1994-02-15
申请号：US767122
申请日：1991-09-27
申请人： Charles E. Narad
发明人： Charles E. Narad
IPC分类号： G06F12/08 , G06F9/308 , G06F9/312 , G06F9/318 , G06F9/46 , G06F12/00 , G06F15/167
CPC分类号： G06F9/526 , G06F9/30018 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3836 , G06F2209/521
摘要： A computer storage register architecture permitting secure atomic access to set or clear one or more particular bits wherein a multiple bit register is disclosed. In the preferred embodiment, a multiplicity of unique addresses is assigned to a multiple bit register. One address constitutes a read address, one address constitutes a clear address, and a third address constitutes a set address. An address decoder decodes the addresses assigned to the register so that only that register is accessed for the associated read, clear, and set operations, respectively. Data having a register position equivalent binary pattern of logical zeros and ones corresponding to particular bit locations of the register to be set or cleared are associated with the set and clear addresses. If the position equivalent binary value of the data associated with the address decoded is a logical one, then the corresponding bit in the register will be set or cleared. Otherwise, the bit remains unchanged.
摘要翻译：一种允许安全原子访问来设置或清除其中公开了多位寄存器的一个或多个特定位的计算机存储寄存器结构。在优选实施例中，多个唯一地址被分配给多位寄存器。一个地址构成读地址，一个地址构成一个清除地址，第三个地址构成一个地址。地址解码器对分配给寄存器的地址进行解码，以便分别仅为相关的读取，清除和设置操作访问该寄存器。具有与要设置或清除的寄存器的特定位位置相对应的具有逻辑零的等效二进制模式的寄存器位置的数据与设置和清除地址相关联。如果与解码的地址相关联的数据的位置等效二进制值为逻辑1，则寄存器中的相应位将被置位或清零。否则，该位保持不变。

9. 发明申请

US20120059956A1 DIRECT MEMORY ACCESS (DMA) TRANSFER OF NETWORK INTERFACE STATISTICS 有权
标题翻译：直接存储器访问（DMA）网络接口统计信息的传输
公开(公告)号：US20120059956A1
公开(公告)日：2012-03-08
申请号：US12942790
申请日：2010-11-09
申请人： Charles E. Narad
发明人： Charles E. Narad
IPC分类号： G06F13/28
CPC分类号： H04L45/60 , G06F13/28 , H04L43/0888
摘要： In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.
摘要翻译：通常，一方面，本发明描述了一种方法，其包括在网络接口处维护网络接口的计量操作的统计。通过从网络接口直接存储器访问由至少一个处理器访问的存储器来传送统计数据。

10. 发明授权

US07313140B2 Method and apparatus to assemble data segments into full packets for efficient packet-based classification 有权
标题翻译：将数据段组合成完整分组的方法和装置，用于有效的基于分组的分类
公开(公告)号：US07313140B2
公开(公告)日：2007-12-25
申请号：US10188087
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047
摘要： A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location. The method may additionally include, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.
摘要翻译：可以在处理器的初始处理阶段中使用一种方法将接收的数据段组装成全分组。该方法可以包括从分组接收多个数据段并且确定多个数据段中的每一个的第一存储位置。该方法还可以包括将多个数据段中的每一个存储在其确定的第一存储位置中，并且为多个数据段中的每一个确定第二存储位置，第二存储位置被逻辑地排序以表示数据段最初发生的顺序在包中。该方法还可以包括将多个数据段中的每一个存储在其确定的第二存储位置中以在将数据段存储在其确定的第二存储位置之后重新组合分组并释放与每个数据段相关联的第一存储位置。该方法可以另外包括在从分组在其确定的第二存储位置中存储分组数据段的结束时，将多个相关数据段的控制传递到处理器中的下一个处理阶段。

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