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1. 发明申请

US20080235558A1 Subsystem and Method for Encoding 64-bit Data Nibble Error Correct and Cyclic-Redundancy Code (CRC) Address Error Detect for Use in a 76-bit Memory Module 有权
标题翻译：用于编码64位数据半字节错误正确和循环冗余码（CRC）的子系统和方法用于76位内存模块的地址错误检测
公开(公告)号：US20080235558A1
公开(公告)日：2008-09-25
申请号：US12132839
申请日：2008-06-04
申请人： Kevin B. Normoyle , Robert G. Hathaway
发明人： Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1016 , G11C5/04 , G11C7/1006 , G11C2029/0409
摘要： A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
摘要翻译：存储器系统提供数据错误检测和校正以及地址错误检测。循环冗余校验（CRC）代码生成地址校验位。使用CRC代码将32位地址压缩为6个地址校验位。 6个地址校验位连接64个数据位和2个标志位，以产生72位校验字。 72位检查字被输入到纠错码（ECC）发生器中，该纠错码产生12个校验位，存储在64位数据位的存储器中。 76位存储器模块可以存储64个数据和12个校验位。可以纠正半字节错误，并且可以检测到所有的半字节+ 1位错误。此外，可以检测位序列中的6位错误。这允许检测地址的6位CRC中的所有错误。 CRC码和ECC是检测复用地址DRAM共同的双位错误的理想选择。

2. 发明授权

US07398449B1 Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module 有权
标题翻译：编码64位数据半字节错误纠错和循环冗余码（CRC）地址错误检测用于76位内存模块
公开(公告)号：US07398449B1
公开(公告)日：2008-07-08
申请号：US11161042
申请日：2005-07-20
申请人： Kevin B. Normoyle , Robert G. Hathaway
发明人： Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： H03M13/00
CPC分类号： G06F11/1016 , G11C5/04 , G11C7/1006 , G11C2029/0409
摘要： A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
摘要翻译：存储器系统提供数据错误检测和校正以及地址错误检测。循环冗余校验（CRC）代码生成地址校验位。使用CRC代码将32位地址压缩为6个地址校验位。 6个地址校验位连接64个数据位和2个标志位，以产生72位校验字。 72位检查字被输入到纠错码（ECC）发生器中，该纠错码产生12个校验位，存储在64位数据位的存储器中。 76位存储器模块可以存储64个数据和12个校验位。可以纠正半字节错误，并且可以检测到所有的半字节+ 1位错误。此外，可以检测位序列中的6位错误。这允许检测地址的6位CRC中的所有错误。 CRC码和ECC是检测复用地址DRAM共同的双位错误的理想选择。

3. 发明授权

US5070475A Floating point unit interface 失效
标题翻译：浮点单元接口
公开(公告)号：US5070475A
公开(公告)日：1991-12-03
申请号：US797856
申请日：1985-11-14
申请人： Kevin B. Normoyle , James M. Guyer , Rainer Vogt , Anthony S. Fong
发明人： Kevin B. Normoyle , James M. Guyer , Rainer Vogt , Anthony S. Fong
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.
摘要翻译：一种数据处理系统，包括与中央处理单元（CPU）连接的浮点计算单元（FPU），其中CPU提供调度控制信号以通知FPU它即将执行浮点宏指令，并提供调度地址，其在提供调度控制信号的相同操作周期期间包括其浮点微指令的起始地址。在FPU中提供缓冲存储器以存储一个解码的宏指令的起始地址，而FPU正在执行先前解码的宏指令的微指令序列。当缓冲区已经存在驻留在其缓冲器中的起始地址时，FPU提供控制信号，以防止CPU提供进一步的调度地址，直到缓冲区为空。还提供了用于同步CPU和FPU操作和数据传输的其他控制信号。

4. 发明授权

US5987081A Method and apparatus for a testable high frequency synchronizer 失效
标题翻译：用于可测试的高频同步器的方法和装置
公开(公告)号：US5987081A
公开(公告)日：1999-11-16
申请号：US884253
申请日：1997-06-27
申请人： Michael A. Csoppenszky , Kevin B. Normoyle , Prakash Narain
发明人： Michael A. Csoppenszky , Kevin B. Normoyle , Prakash Narain
IPC分类号： G06F5/06 , H04L7/00 , H04L7/02
CPC分类号： G06F5/06 , H04L7/0012 , H04L7/02 , H04L7/0004
摘要： A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.
摘要翻译：在系统测试期间，使用包括在一系列触发器中的同步器来确定性地在时钟域之间传送数据。在较高时钟频率下操作的时钟域中的触发器具有时钟使能信号。时钟使能信号被定义为使得较快时钟信号的使能的上升时钟沿与较慢时钟信号的下降沿近似对准。这种近似对准提供了较慢时钟的一个半周期的定时窗口，以便数据在采样之前在更快的时钟域中稳定在触发器的输入端。这确保数据的确定性传输。数据流控制电路可用于向较快的时钟域提供就绪信号，以指示同步器可用于传送同步信号。测试完成后，同步器可以以应用模式工作，其中一个或多个时钟使能信号被设置为连续的高电平以最小化等待时间。

5. 发明授权

US5907485A Method and apparatus for flow control in packet-switched computer system 失效
标题翻译：分组交换计算机系统中流控制的方法和装置
公开(公告)号：US5907485A
公开(公告)日：1999-05-25
申请号：US414875
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F9/46 , G06F13/24 , G05B15/00
CPC分类号： G06F9/546 , G06F13/24
摘要： This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.
摘要翻译：本发明描述了一种用于分组交换单处理器和多处理器计算机系统的链路链路流控制方法，其使系统资源利用率和吞吐量最大化，并最小化系统等待时间。计算机系统包括一个或多个主接口，一个或多个从接口和互连系统控制器，其为每个主接口提供专用事务请求队列，并且控制事务到每个从接口的转发。主接口跟踪系统控制器中专用队列中的请求数，系统控制器跟踪每个从接口队列中的请求数。主接口和系统控制器都知道其下游队列的最大容量，并且不会比下游队列可以容纳更多的事务请求。来自下游队列的确认向发送方指示在其中存在另一个事务的空间。因此，尝试将请求发送到已满的队列时，不会浪费任何系统资源。

6. 发明授权

US5852608A Structure and method for bi-directional data transfer between asynchronous clock domains 失效
标题翻译：异步时钟域之间双向数据传输的结构和方法
公开(公告)号：US5852608A
公开(公告)日：1998-12-22
申请号：US659729
申请日：1996-06-06
申请人： Michael A. Csoppenszky , Kevin B. Normoyle
发明人： Michael A. Csoppenszky , Kevin B. Normoyle
IPC分类号： G06F5/06 , G06F12/00
CPC分类号： G06F5/065
摘要： Bi-directional data transfers between a first system and a second system, which have asynchronous clock domains, are performed using a single dual-port memory. A direction control circuit, which is connected between the first and second systems, determines the desired direction of data transfer and generates one or more direction signals representative of this direction. A write control circuit is coupled to receive a direction control signal, as well as write control signals from the first and second systems. Similarly, a read control signal is coupled to receive a direction control signal, as well as read control signals from the first and second systems. If data transfer is to proceed from the first system to the second system, the write control circuit gives the first system control over the write port of the dual-port memory, and the read control circuit gives the second system control over the read port of the dual-port memory in response to the direction control signals. Conversely, if data transfer is to proceed from the second system to the first system, the write control circuit gives the second system control over the write port of the dual-port memory, and the read control circuit gives the first system control over the read port of the dual-port memory in response to the direction control signals.
摘要翻译：具有异步时钟域的第一系统和第二系统之间的双向数据传输使用单个双端口存储器执行。连接在第一和第二系统之间的方向控制电路确定期望的数据传送方向，并产生代表该方向的一个或多个方向信号。写入控制电路被耦合以接收方向控制信号，以及来自第一和第二系统的写入控制信号。类似地，读控制信号被耦合以接收方向控制信号，以及从第一和第二系统读取控制信号。如果从第一系统进行数据传输到第二系统，则写入控制电路对双端口存储器的写入端口进行第一系统控制，并且读取控制电路对第二系统的读取端口进行第二系统控制响应方向控制信号的双端口存储器。相反，如果数据传输从第二系统进行到第一系统，则写入控制电路对双端口存储器的写入端口进行第二系统控制，并且读取控制电路对读取的第一系统进行控制端口的双端口存储器响应方向控制信号。

7. 发明授权

US08099651B2 Subsystem and method for encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use in a 76-bit memory module 有权
标题翻译： 64位数据半字节错误校正和循环冗余码（CRC）地址错误检测用于76位内存模块的子系统和方法
公开(公告)号：US08099651B2
公开(公告)日：2012-01-17
申请号：US12132839
申请日：2008-06-04
申请人： Kevin B. Normoyle , Robert G. Hathaway
发明人： Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1016 , G11C5/04 , G11C7/1006 , G11C2029/0409
摘要： A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
摘要翻译：存储器系统提供数据错误检测和校正以及地址错误检测。循环冗余校验（CRC）代码生成地址校验位。使用CRC代码将32位地址压缩为6个地址校验位。 6个地址校验位连接64个数据位和2个标志位，以产生72位校验字。 72位检查字被输入到纠错码（ECC）发生器中，该纠错码产生12个校验位，存储在64位数据位的存储器中。 76位存储器模块可以存储64个数据和12个校验位。可以纠正半字节错误，并且可以检测到所有的半字节+ 1位错误。此外，可以检测位序列中的6位错误。这允许检测地址的6位CRC中的所有错误。 CRC码和ECC是检测复用地址DRAM共同的双位错误的理想选择。

8. 发明授权

US07366847B2 Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag 有权
标题翻译：可扩展请求者过滤管道上的分布式高速缓存一致性，使用来自中央监听标签的排序消息从其他请求者过滤器管道累积无效确认
公开(公告)号：US07366847B2
公开(公告)日：2008-04-29
申请号：US11307413
申请日：2006-02-06
申请人： David A. Kruckemyer , Kevin B. Normoyle , Robert G. Hathaway
发明人： David A. Kruckemyer , Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： G06F12/00
CPC分类号： G06F12/082 , G06F12/0828
摘要： A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having a copy of a requested cache line. The central coherency controller sends an ordering message to the requesting filter pipe. The ordering message has an invalidate count indicating the number of sharing caches. Each sharing cache receives an invalidation message from the central coherency controller, invalidates its copy of the cache line, and sends an invalidation acknowledgement message to the requesting filter pipe. The requesting filter pipe decrements the invalidate count until all sharing caches have acknowledged invalidation. All ordering, data, and invalidation acknowledgement messages must be received by the requesting filter pipe before loading the data into its cache.
摘要翻译：多处理器，多缓存系统具有过滤器管道，其存储发送到中央一致性控制器的请求消息的条目。中央一致性控制器使用一致性规则对来自过滤器管道的请求进行排序，但不跟踪完成无效。中央一致性控制器读取窥探标签以识别具有所请求的高速缓存行的副本的共享高速缓存。中央一致性控制器向请求过滤管发送排序消息。排序消息具有指示共享缓存数量的无效计数。每个共享缓存从中央一致性控制器接收到无效消息，使其高速缓存行的副本无效，并向请求的过滤器管道发送无效确认消息。请求过滤管道减少无效计数，直到所有共享缓存都确认无效。在将数据加载到其缓存中之前，请求过滤器管道必须接收所有排序，数据和无效确认消息。

9. 发明授权

US07337339B1 Multi-level power monitoring, filtering and throttling at local blocks and globally 有权
标题翻译：在本地区域和全球进行多级电源监控，过滤和调节
公开(公告)号：US07337339B1
公开(公告)日：2008-02-26
申请号：US11162578
申请日：2005-09-15
申请人： Jack H. Choquette , Kevin B. Normoyle , Elias Atmeh , Scott D. Sellers , Murali Sundaresan , Manuel Gautho
发明人： Jack H. Choquette , Kevin B. Normoyle , Elias Atmeh , Scott D. Sellers , Murali Sundaresan , Manuel Gautho
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.
摘要翻译：多处理器芯片的电源管理包括一个集中的全球电源管理器，用于监控整个芯片的全球电源以及本地电源管理器。本地电源管理器管理本地块（如处理器内核，高速缓存和内存控制器）的电源。当本地块执行指令或访问存储器时，在本地功率估计表中生成并查找事件。该事件的局部功率估计被发送到全局功率管理器，其总和从所有本地块接收的所有本地功率估计。生成指数移动平均值（EMA），并与全局功率阈值进行比较。当全球电力超过阈值时，本地目标将发送给能够管理并产生并必须保持在本地目标下的局部功率平均值的电源管理员。本地电源管理器节流本地电源，以便在超出当地目标时降低电力。

10. 发明授权

US06477622B1 Simplified writeback handling 有权
标题翻译：简化回写处理
公开(公告)号：US06477622B1
公开(公告)日：2002-11-05
申请号：US09670856
申请日：2000-09-26
申请人： Kevin B. Normoyle , Meera Kasinathan , Rajasekhar Cherabuddi
发明人： Kevin B. Normoyle , Meera Kasinathan , Rajasekhar Cherabuddi
IPC分类号： G06F1200
CPC分类号： G06F12/0804
摘要： The main cache of a processor in a multiprocessor computing system is coupled to receive writeback data during writeback operations. In one embodiment, during writeback operations, e.g., for a cache miss, dirty data in the main cache is merged with modified data from an associated write cache, and the resultant writeback data line is loaded into a writeback buffer. The writeback data is also written back into the main cache, and is maintained in the main cache until replaced by new data. Subsequent requests (i.e., snoops) for the data are then serviced from the main cache, rather than from the writeback buffer. In some embodiments, further modifications of the writeback data in the main cache are prevented. The writeback data line in the main cache remains valid until read data for the cache miss is returned, thereby ensuring that the read address reaches the system interface for proper bus ordering before the writeback line is lost. In one embodiment, the writeback operation is paired with the read operation for the cache miss to ensure that upon completion of the read operation, the writeback address has reached the system interface for bus ordering, thereby maintaining cache coherency while allowing requests to be serviced from the main cache.
摘要翻译：多处理器计算系统中的处理器的主缓存被耦合以在回写操作期间接收回读数据。在一个实施例中，在回写操作期间，例如，对于高速缓存未命中，主缓存器中的脏数据与来自相关联的写入高速缓存的修改的数据合并，并且所得到的写回数据行被加载到写回缓冲器中。写回数据也被写回到主缓存中，并保存在主缓存中，直到被新数据替换为止。然后，从主缓存器而不是从回写缓冲器来服务数据的后续请求（即，窥探）。在一些实施例中，防止主缓存中的回写数据的进一步修改。主缓存中的回写数据线在返回高速缓存未命中的读取数据之前保持有效，从而确保读地址到达系统接口以在回写行丢失之前进行正确的总线排序。在一个实施例中，写回操作与用于高速缓存未命中的读取操作配对，以确保在完成读取操作时，回写地址已经到达用于总线排序的系统接口，从而保持高速缓存一致性，同时允许从主缓存。

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