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1. 发明授权

US5530809A Router for parallel computer including arrangement for redirecting messages 失效
标题翻译：用于并行计算机的路由器，包括用于重定向消息的布置
公开(公告)号：US5530809A
公开(公告)日：1996-06-25
申请号：US181711
申请日：1994-01-14
申请人： David C. Douglas , Charles E. Leiserson , Bradley C. Kuszmaul , Shaw-Wen Yang , W. Daniel Hillis , David Wells , Carl R. Feynman , Bruce J. Walker , Brewster Kahle
发明人： David C. Douglas , Charles E. Leiserson , Bradley C. Kuszmaul , Shaw-Wen Yang , W. Daniel Hillis , David Wells , Carl R. Feynman , Bruce J. Walker , Brewster Kahle
IPC分类号： G06F15/16 , G06F11/00 , G06F11/08 , G06F11/22 , G06F15/173 , G06F15/80 , G06F15/163
CPC分类号： G06F15/17381 , G06F11/08 , G06F11/22 , G06F11/324 , G06F15/17343 , H04L45/48 , H04L49/35 , H04L49/555 , G06F2201/88
摘要： A digital computer comprising a plurality of message generating nodes interconnected by a routing network. The routing network transfers messages among the message generating elements in accordance with address information identifying a destination message generating element. Each message generating node includes a message data generator and a network interface. The message data generator generates message data items each including an address data portion comprising a destination identifier. The network interface includes a message generator and an address translation table, the table including a plurality of entries identifying, for at least one destination identifier, a translated destination identifier. The message generator, in response to the receipt of a message data item from the message data generator, generates a message for transmission to the routing network. In generating the message, the message generator performs an address translation operation in connection with the address data and the contents of the address translation table to generate updated address data which it uses data in connection with generating address information for the message.
摘要翻译：一种数字计算机，包括由路由网络互连的多个消息生成节点。路由网络根据识别目的地消息生成元素的地址信息在消息生成元件之间传送消息。每个消息生成节点包括消息数据生成器和网络接口。消息数据生成器生成包括包括目的地标识符的地址数据部分的消息数据项。网络接口包括消息发生器和地址转换表，该表包括多个条目，用于为至少一个目的地标识符标识已翻译的目的地标识符。消息生成器响应于从消息数据生成器接收到消息数据项，生成用于传输到路由网络的消息。在生成消息时，消息生成器执行与地址数据和地址转换表的内容相关的地址转换操作，以生成更新的地址数据，其使用与为消息生成地址信息相结合的数据。

2. 发明授权

US5118975A Digital clock buffer circuit providing controllable delay 失效
标题翻译：数字时钟缓冲电路提供可控延时
公开(公告)号：US5118975A
公开(公告)日：1992-06-02
申请号：US489079
申请日：1990-03-05
申请人： W. Daniel Hillis , Zahi S. Abuhamdeh , Bradley C. Kuszmaul , Jon P. Wade , Shaw-Wen Yang
发明人： W. Daniel Hillis , Zahi S. Abuhamdeh , Bradley C. Kuszmaul , Jon P. Wade , Shaw-Wen Yang
IPC分类号： H03K5/135 , G06F1/10 , G11C11/407 , H03L7/00 , H03L7/081 , H03L7/087 , H03L7/089
CPC分类号： G06F1/10 , H03L7/0814 , H03L7/087 , H03L7/089
摘要： A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

3. 发明授权

US06219775B1 Massively parallel computer including auxiliary vector processor 失效
标题翻译：大容量并行计算机包括辅助矢量处理器
公开(公告)号：US06219775B1
公开(公告)日：2001-04-17
申请号：US09040747
申请日：1998-03-18
申请人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
发明人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
IPC分类号： G06F702
CPC分类号： G06F15/8092 , G06F15/17381 , G06F15/8084 , G06F21/52
摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.
摘要翻译：大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。每个处理节点包括用于在网络上传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。节点处理器进一步通过接口控制网络上的数据传输。辅助处理器连接到存储器模块和节点处理器。响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。

4. 发明授权

US5872987A Massively parallel computer including auxiliary vector processor 失效
标题翻译：大容量并行计算机包括辅助矢量处理器
公开(公告)号：US5872987A
公开(公告)日：1999-02-16
申请号：US714635
申请日：1996-09-16
申请人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
发明人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
IPC分类号： G06F15/173 , G06F15/78 , G06F15/80 , G06F7/02
CPC分类号： G06F15/8092 , G06F15/17381 , G06F15/8084 , G06F21/52
摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.
摘要翻译：大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。每个处理节点包括用于从网络传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。节点处理器进一步通过接口控制网络上的数据传输。辅助处理器连接到存储器模块和节点处理器。响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。

5. 发明授权

US5390298A Parallel computer system including arrangement for quickly draining messages from message router 失效
标题翻译：并行计算机系统，包括用于从消息路由器快速排出消息的布置
公开(公告)号：US5390298A
公开(公告)日：1995-02-14
申请号：US183217
申请日：1994-01-14
申请人： Bradley C. Kuszmaul , Charles E. Leiserson , Shaw-Wen Yang , Carl R. Feynman , W. Daniel Hillis , David Wells , Cynthia J. Spiller
发明人： Bradley C. Kuszmaul , Charles E. Leiserson , Shaw-Wen Yang , Carl R. Feynman , W. Daniel Hillis , David Wells , Cynthia J. Spiller
IPC分类号： G06F15/16 , G06F11/00 , G06F11/08 , G06F11/22 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17381 , G06F11/08 , G06F11/22 , G06F11/324 , G06F15/17343 , H04L45/48 , H04L49/35 , H04L49/555 , G06F2201/88
摘要： A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion. In a second mode, the router node couple received messages to predetermined ones of the router nodes or processors connected thereto, the predetermined ones of said router nodes or processors being selected to facilitate transfer of a message to a nearby processor to facilitate the rapid emptying of the routing network of messages. A control element controls the router nodes to enable them to operate in the first mode or second mode generally contemporaneously.
摘要翻译：包括处理器阵列和路由网络的计算机。处理器阵列中的处理器产生用于通过路由网络传送的消息，每个消息包括标识从源，消息处理器到目的地处理器的路径的路径标识符部分。路由网络包括多个互连的路由器节点，所述路由器节点中的至少一些连接到处理器以从其接收消息并向其发送消息。每个路由器节点以多种模式操作。在第一模式中，路由器节点根据路径标识符部分将接收到的消息耦合到与其连接的路由器节点，从而沿着其路径标识符部分中标识的路径传送每个相应的消息。在第二模式中，路由器节点将接收到的消息耦合到连接到其上的路由器节点或处理器中的预定路由器节点，所选择的所述路由器节点或处理器中的预定路由器节点或处理器便于将消息传送到附近的处理器，以便于快速排空消息的路由网络。控制元件控制路由器节点，使得它们能够在第一模式或第二模式下同时运行。

6. 发明授权

US5680550A Digital computer for determining a combined tag value from tag values selectively incremented and decremented reflecting the number of messages transmitted and not received 失效
标题翻译：用于从标签值确定组合标签值的数字计算机选择性地递增和减少，反映发送和未接收的消息的数量
公开(公告)号：US5680550A
公开(公告)日：1997-10-21
申请号：US388031
申请日：1995-02-13
申请人： Bradley C. Kuszmaul , Charles E. Leiserson , Shaw-Wen Yang , Carl R. Feynman , W. Daniel Hillis , David C. Douglas
发明人： Bradley C. Kuszmaul , Charles E. Leiserson , Shaw-Wen Yang , Carl R. Feynman , W. Daniel Hillis , David C. Douglas
IPC分类号： G06F15/16 , G06F11/00 , G06F11/08 , G06F11/22 , G06F15/173 , G06F15/80 , G06F13/00 , G06F3/00
CPC分类号： G06F15/17381 , G06F11/08 , G06F11/22 , G06F11/324 , G06F15/17343 , H04L45/48 , H04L49/35 , H04L49/555 , G06F2201/88
摘要： A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.
摘要翻译：数字计算机包括多个处理元件，命令处理器，诊断处理器和通信网络。处理元件各自执行与命令相关的数据处理和数据通信操作。处理元件还响应诊断操作请求执行诊断操作，并响应于此提供诊断结果。命令处理器为处理元件生成命令，并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。诊断处理器产生诊断请求。通信网络包括三个元件，包括数据路由器，控制网络和诊断网络。数据路由器连接到处理元件，以便在数据通信操作期间便于它们之间的数据传输。控制网络连接到处理元件和命令处理器，用于将命令从命令处理器传送到处理元件。连接到处理元件的诊断网络，命令处理器和诊断处理器，用于将诊断请求从诊断处理器传送到处理元件和命令处理器，并将诊断结果从处理元件和命令处理器传送到诊断处理器。

7. 发明授权

US5333268A Parallel computer system 失效
标题翻译：并行计算机系统
公开(公告)号：US5333268A
公开(公告)日：1994-07-26
申请号：US946242
申请日：1992-09-16
申请人： David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Bradley C. Kuszmaul , Charles E. Leiserson , David S. Wells , Monica C. Wong , Shaw-Wen Yang , Robert C. Zak
发明人： David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Bradley C. Kuszmaul , Charles E. Leiserson , David S. Wells , Monica C. Wong , Shaw-Wen Yang , Robert C. Zak
IPC分类号： G06F15/16 , G06F11/00 , G06F11/08 , G06F11/22 , G06F15/173 , G06F15/80
CPC分类号： G06F15/17381 , G06F11/08 , G06F11/22 , G06F11/324 , G06F15/17343 , H04L45/48 , H04L49/35 , H04L49/555 , G06F2201/88
摘要： A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.
摘要翻译：数字计算机包括多个处理元件，命令处理器，诊断处理器和通信网络。处理元件各自执行与命令相关的数据处理和数据通信操作。处理元件还响应诊断操作请求执行诊断操作，并响应于此提供诊断结果。命令处理器为处理元件生成命令，并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。诊断处理器产生诊断请求。通信网络包括三个元件，包括数据路由器，控制网络和诊断网络。数据路由器连接到处理元件，以便在数据通信操作期间便于它们之间的数据传输。控制网络连接到处理元件和命令处理器，用于将命令从命令处理器传送到处理元件。连接到处理元件的诊断网络，命令处理器和诊断处理器，用于将诊断请求从诊断处理器传送到处理元件和命令处理器，并将诊断结果从处理元件和命令处理器传送到诊断处理器。

8. 发明授权

US5265207A Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a plurality of destination processors and combining responses 失效
标题翻译：并行计算机系统，包括用于将消息从源处理器传送到多个目的地处理器中的选择的处理器并组合响应的布置
公开(公告)号：US5265207A
公开(公告)日：1993-11-23
申请号：US45549
申请日：1993-04-08
申请人： Robert C. Zak , Charles E. Leiserson , Bradley C. Kuzmaul , Shaw-Wen Yang , W. Daniel Hillis , David C. Douglas , David Potter
发明人： Robert C. Zak , Charles E. Leiserson , Bradley C. Kuzmaul , Shaw-Wen Yang , W. Daniel Hillis , David C. Douglas , David Potter
IPC分类号： G06F11/00 , G06F11/08 , G06F11/22 , G06F15/173 , G06F13/00
CPC分类号： G06F15/17343 , G06F11/08 , G06F11/22 , H04L49/35 , G06F2201/88
摘要： A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor, generates messages, each including an address defining a path through the interconnection network from the source processor to one or more of the processors which are to receive the message as destination processors. The interconnection network establishes, in response to a message from the source processor, a path in accordance with the address from the source processor in a downstream direction to the destination processors thereby to facilitate transfer of the message to the destination processors. Each destination processor generates response indicia in response to a message. The interconnection network receives the response indicia from the destination processor(s) and generates, in response, consolidated response indicia which it transfers in an upstream direction to the source processor.
摘要翻译：一种并行计算机，包括多个处理器和用于在处理器之间传送消息的互连网络。作为源处理器的至少一个处理器生成消息，每个消息包括定义通过互连网络从源处理器到将要作为目的地处理器接收消息的一个或多个处理器的路径的地址。互连网络响应于来自源处理器的消息，建立根据来自源处理器的下行方向的地址到目的地处理器的路径，从而便于将消息传送到目的地处理器。每个目的地处理器响应于消息产生响应标记。互连网络从目的地处理器接收响应标记，并作为响应产生其在上游方向上传送到源处理器的综合响应标记。

9. 发明授权

US5958019A Multiprocessing system configured to perform synchronization operations 失效
标题翻译：多处理系统配置为执行同步操作
公开(公告)号：US5958019A
公开(公告)日：1999-09-28
申请号：US674328
申请日：1996-07-01
申请人： Erik E. Hagersten , Robert C. Zak, Jr. , Shaw-Wen Yang , Aleksandr Guzovskiy , William A. Nesheim , Monica C. Wong-Chan , Hien Nguyen
发明人： Erik E. Hagersten , Robert C. Zak, Jr. , Shaw-Wen Yang , Aleksandr Guzovskiy , William A. Nesheim , Monica C. Wong-Chan , Hien Nguyen
IPC分类号： G06F9/52 , G06F9/46 , G06F12/08 , G06F13/42
CPC分类号： G06F9/52 , G06F12/0828
摘要： When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency activity is completed. Therefore, the computer system may employ asynchronous operations. The synchronization operations may be used when needed to guarantee global completion of one or more prior asynchronous operations. In one embodiment, the synchronization operation is placed into a queue within the system interface. When the synchronization operation reaches the head of the queue, it may be initiated within the system interface. The system interface further includes a request agent comprising multiple control units, each of which may concurrently service coherency activity with respect to a different transaction. Furthermore, the system interface includes a synchronization control vector register which stores a bit for each control unit. Upon initiation of the synchronization operation within the system interface, bits corresponding to those control units which are performing coherency activity (i.e. those which are not idle) are set while other bits are cleared. As each control unit returns to the idle state, the corresponding bit is cleared as well. Once all the bits within the synchronization control vector register are cleared, the coherency activity which was outstanding when the synchronization operation was initiated is complete. The synchronization operation may then be completed.
摘要翻译：当计算机系统内的处理器执行同步操作时，节点内的系统接口会延迟来自处理器的后续事务，直到完成一致的一致性活动。因此，计算机系统可以采用异步操作。当需要保证一个或多个在先的异步操作的全局完成时，可以使用同步操作。在一个实施例中，同步操作被放置在系统接口内的队列中。当同步操作到达队列的头部时，可以在系统界面内启动。该系统接口还包括一个包含多个控制单元的请求代理，每个控制单元可以相对于不同的事务同时提供一致性活动。此外，系统接口包括存储每个控制单元的位的同步控制向量寄存器。在系统接口中启动同步操作之后，在执行一致性活动的那些控制单元（即那些不空闲的）的对应的位被设置，而其它位被清除。当每个控制单元返回到空闲状态时，相应的位也被清除。一旦清除了同步控制向量寄存器中的所有位，完成了同步操作启动时未完成的一致性活动。然后可以完成同步操作。

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