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1. 发明授权

US5118975A Digital clock buffer circuit providing controllable delay 失效
标题翻译：数字时钟缓冲电路提供可控延时
公开(公告)号：US5118975A
公开(公告)日：1992-06-02
申请号：US489079
申请日：1990-03-05
申请人： W. Daniel Hillis , Zahi S. Abuhamdeh , Bradley C. Kuszmaul , Jon P. Wade , Shaw-Wen Yang
发明人： W. Daniel Hillis , Zahi S. Abuhamdeh , Bradley C. Kuszmaul , Jon P. Wade , Shaw-Wen Yang
IPC分类号： H03K5/135 , G06F1/10 , G11C11/407 , H03L7/00 , H03L7/081 , H03L7/087 , H03L7/089
CPC分类号： G06F1/10 , H03L7/0814 , H03L7/087 , H03L7/089
摘要： A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

2. 发明授权

US06219775B1 Massively parallel computer including auxiliary vector processor 失效
标题翻译：大容量并行计算机包括辅助矢量处理器
公开(公告)号：US06219775B1
公开(公告)日：2001-04-17
申请号：US09040747
申请日：1998-03-18
申请人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
发明人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
IPC分类号： G06F702
CPC分类号： G06F15/8092 , G06F15/17381 , G06F15/8084 , G06F21/52
摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.
摘要翻译：大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。每个处理节点包括用于在网络上传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。节点处理器进一步通过接口控制网络上的数据传输。辅助处理器连接到存储器模块和节点处理器。响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。

3. 发明授权

US5872987A Massively parallel computer including auxiliary vector processor 失效
标题翻译：大容量并行计算机包括辅助矢量处理器
公开(公告)号：US5872987A
公开(公告)日：1999-02-16
申请号：US714635
申请日：1996-09-16
申请人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
发明人： Jon P. Wade , Daniel R. Cassiday , Robert D. Lordi , Guy Lewis Steele, Jr. , Margaret A. St. Pierre , Monica C. Wong-Chan , Zahi S. Abuhamdeh , David C. Douglas , Mahesh N. Ganmukhi , Jeffrey V. Hill , W. Daniel Hillis , Scott J. Smith , Shaw-Wen Yang , Robert C. Zak, Jr.
IPC分类号： G06F15/173 , G06F15/78 , G06F15/80 , G06F7/02
CPC分类号： G06F15/8092 , G06F15/17381 , G06F15/8084 , G06F21/52
摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.
摘要翻译：大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。每个处理节点包括用于从网络传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。节点处理器进一步通过接口控制网络上的数据传输。辅助处理器连接到存储器模块和节点处理器。响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。

4. 发明申请

US20090255513A1 Deformable chamber-based homogeneous charge combustion ignition (HCCI) engine and generator 失效
标题翻译：可变形腔室均质充气燃烧点火（HCCI）发动机和发电机
公开(公告)号：US20090255513A1
公开(公告)日：2009-10-15
申请号：US12082325
申请日：2008-04-11
申请人： Robert C. Zak , Jon P. Wade
发明人： Robert C. Zak , Jon P. Wade
IPC分类号： F02B71/04 , F02B71/00 , F02D35/02
CPC分类号： F02B75/36 , F01L3/205 , F01L9/04 , F02B1/12 , F02D41/3035 , Y02T10/128
摘要： A reciprocating internal combustion engine is based on Homogenous Charge Compression Ignition (HCCI) that occurs in a deformable, resonant combustion chamber and that is coupled mechanically to efficient, resonant, electromechanical transducers acting as motors and generators. The mechanical coupling also implements fuel/air intake valves and exhaust valves. Embedded sensors allow an electronic control system to start the engine and thereafter to maintain operational configuration of the moving components in response to the effects of imperfect mechanical fabrication and/or assembly and dynamic changes in mechanical properties of the materials with run-time temperature and engine life.
摘要翻译：往复式内燃机基于均质充量压缩点火（HCCI），其发生在可变形的共振燃烧室中，并且机械耦合到用作电动机和发电机的有效的共振的机电换能器。机械联轴器还实现了燃油/进气阀和排气阀。嵌入式传感器允许电子控制系统启动发动机，此后可以响应于不完美的机械制造和/或组装以及具有运行时温度和发动机的材料的机械性能的动态变化的影响来维持运动部件的运行配置生活。

5. 发明授权

US5878227A System for performing deadlock free message transfer in cyclic multi-hop digital computer network using a number of buffers based on predetermined diameter 失效
标题翻译：用于使用基于预定直径的多个缓冲器在循环多跳数字计算机网络中执行无死锁消息传送的系统
公开(公告)号：US5878227A
公开(公告)日：1999-03-02
申请号：US674277
申请日：1996-07-01
申请人： Jon P. Wade , Steven K. Heller
发明人： Jon P. Wade , Steven K. Heller
IPC分类号： H04L12/42 , H04L12/56 , G06F13/00
CPC分类号： H04L12/42 , H04L12/56
摘要： In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node. At least one of the switching nodes has a plurality of buffers for buffering a corresponding plurality of message packets that it (that is, the at least one of the switching nodes) receives from another of said switching nodes during a message transfer operation, which ensures that deadlock does not occur during the message transfer operation.
摘要翻译：总之，本发明提供了一种新的消息分组传送系统，其可以在例如多处理器计算机系统中使用。消息分组传送系统包括通过通信链路互连的多个交换节点，以限定具有预定直径的至少一个循环分组传送路径。交换节点可以连接到例如数字数据处理器和存储器，以在多处理器计算机系统中形成处理节点，和/或连接到包含在消息分组中的数字数据的其他源和目的地。交换节点将作为相应源交换节点的交换节点中的相应一个的消息分组作为相应的目的地交换节点传送到交换节点中的相应一个。交换节点中的至少一个具有多个缓冲器，用于在消息传送操作期间缓冲它（即至少一个交换节点）从另一个所述交换节点接收的对应的多个消息分组，这确保在邮件传输操作期间不会发生死锁。

6. 发明申请

US20110100430A1 Hybrid photovoltaic and thermionic energy converter 审中-公开
标题翻译：混合光伏和热电能转换器
公开(公告)号：US20110100430A1
公开(公告)日：2011-05-05
申请号：US12590304
申请日：2009-11-05
申请人： Robert C. Zak, JR. , Jon P. Wade
发明人： Robert C. Zak, JR. , Jon P. Wade
IPC分类号： H01L31/058
CPC分类号： H01J45/00 , H01G9/2022 , H02S10/10 , Y02E10/542
摘要： The current invention uses a combination of technologies from dye-sensitized solar cells, and from thermionic generators, to form a unique, efficient, broad spectrum solar radiation to electric power converter. Light passing through the cell first passes through a dye-sensitized matrix of nanoporous semiconductor. Light within the absorption spectrum of the dye is absorbed and converted into electrons which are injected into the conduction band of the semiconductor matrix. Light, which is not absorbed by the dye, passes on to cathode. The cathode is heated upon absorbing the incoming radiation. At a temperature dependent on the work function of the cathode, the cathode emits electrons thermionically, thereby cooling the cathode. These electrons replenish the electrons in the dye, thus completing the flow of current between cathode and anode. The hot cathode is thermally isolated from portions of the device at ambient temperature, thereby minimizing parasitic thermal loss. The device produces electricity similar to a two junction photovoltaic cell in that the anode is added to the cathode voltage.
摘要翻译：本发明使用来自染料敏化太阳能电池和热电子发生器的技术的组合，以形成独特的，有效的广谱太阳辐射到电力转换器。首先通过细胞的光通过纳米多孔半导体的染料敏化基质。在染料的吸收光谱内的光被吸收并转换成注入到半导体矩阵的导带中的电子。不被染料吸收的光传递到阴极。阴极在吸收进入的辐射时被加热。在取决于阴极功函数的温度下，阴极发射热电子，从而冷却阴极。这些电子补充染料中的电子，从而完成阴极和阳极之间的电流流动。热阴极在环境温度下与器件的部分热隔离，从而最小化寄生热损失。该装置产生类似于二结光伏电池的电力，因为将阳极添加到阴极电压。

7. 再颁专利

USRE38650E1 System for performing deadlock free message transfer in cyclic multi-hop digital computer network using a number of buffers based on predetermined diameter 有权
标题翻译：用于使用基于预定直径的多个缓冲器在循环多跳数字计算机网络中执行无死锁消息传送的系统
公开(公告)号：USRE38650E1
公开(公告)日：2004-11-09
申请号：US09798283
申请日：2001-03-02
申请人： Jon P. Wade , Steven K. Heller
发明人： Jon P. Wade , Steven K. Heller
IPC分类号： G06E1300
CPC分类号： H04L12/42 , H04L12/56
摘要： In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node. At least one of the switching nodes has a plurality of buffers for buffering a corresponding plurality of message packets that it (that is, the at least one of the switching nodes) receives from another of said switching nodes during a message transfer operation, which ensures that deadlock does not occur during the message transfer operation.

8. 发明授权

US5287386A Differential driver/receiver circuit 失效
标题翻译：差分驱动器/接收器电路
公开(公告)号：US5287386A
公开(公告)日：1994-02-15
申请号：US676132
申请日：1991-03-27
申请人： Jon P. Wade , David S. Wells
发明人： Jon P. Wade , David S. Wells
IPC分类号： H03K3/356 , H03K5/02 , H03K17/16 , H03K17/687 , H03K17/693 , H03K19/003 , H04B3/50 , H04L25/02 , H04L25/03 , H04B3/00
CPC分类号： H04L25/028 , H03K17/164 , H03K17/693 , H03K3/356147 , H03K5/023 , H04L25/0272 , H04L25/0292 , H04L25/03834
摘要： A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal. The receiver circuit, during normal receiving operations, generates true and complement signals in response to the differential receive signal pair. During a test mode, the receiver circuit, in separate steps, compares the voltage levels of the true and complement receive signals to threshold voltages and generates an error signal if the selected true or complement receive signal does not have the proper relationship to the voltage level of the threshold voltage.
摘要翻译：一种用于发送和接收差分信号对的新的驱动器电路和接收器电路。驱动器电路包括串联产生差分信号对的真和补码信号产生元件。每个真实和补码信号产生元件包括高增益元件和至少一个低增益元件。延迟电路响应于真实和补码数据信号，用于迭代地控制每个信号产生元件的高增益元件和低增益元件以产生差分信号对，延迟电路控制高增益元件相对于低增益元件的延迟，从而减少差分信号对中的振铃。接收器电路接收差分接收信号对，其包括在一对输入线上具有选定条件的真和补码接收信号，并产生真实和补码数据信号。在正常接收操作期间，接收机电路响应于差分接收信号对而产生真实和补码信号。在测试模式期间，接收器电路在单独的步骤中，将真实和补码接收信号的电压电平与阈值电压进行比较，并且如果所选择的真或接收信号与电压电平没有正确关系，则产生误差信号的阈值电压。

9. 发明授权

US4831585A Four transistor cross-coupled bitline content addressable memory 失效
标题翻译：四个晶体管交叉耦合位线内容可寻址存储器
公开(公告)号：US4831585A
公开(公告)日：1989-05-16
申请号：US115585
申请日：1987-10-26
申请人： Jon P. Wade , Charles G. Sodini
发明人： Jon P. Wade , Charles G. Sodini
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory cell comprises two storage IGFETs connected between a Match line and respective bitlines. Stored potentials are applied to the gates of the IGFETs through Write IGFETs which are cross coupled to the bitlines. The cross-coupling results in a larger storage capacitance and reduced degenerative capacitive coupling. This improves the speed and noise immunity of the cell. The memory cell is fabricated with three primary levels: a lower level of semiconductor material in which the source, drain and channel of each FET is formed, a center level of conductive material in which the Match and Write lines and the gates of the FETs are formed and an upper level in which the bitlines are formed. The center and lower levels are interconnected at buried contacts.
摘要翻译：内容可寻址存储器单元包括连接在匹配线和相应位线之间的两个存储IGFET。通过与交叉耦合到位线的写入IGFET将存储的电位施加到IGFET的栅极。交叉耦合导致更大的存储电容和减小的退化电容耦合。这提高了电池的速度和抗噪声能力。存储单元由三个主要级别制成：其中形成每个FET的源极，漏极和沟道的较低级别的半导体材料，导体材料的中心电平，其中匹配和写入线和FET的栅极为形成，并且形成位线的上层。中心和下层在埋地接触处相互连接。

10. 发明授权

US4799192A Three-transistor content addressable memory 失效
标题翻译：三晶体管内存可寻址存储器
公开(公告)号：US4799192A
公开(公告)日：1989-01-17
申请号：US901514
申请日：1986-08-28
申请人： Jon P. Wade , Charles G. Sodini
发明人： Jon P. Wade , Charles G. Sodini
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory cell includes two storage field effect transistors of opposite conductivity type with their gates connected in common. A single write transistor is connected between the common gates and a bitline for storing a potential on the gates from the bitline.
摘要翻译：内容可寻址存储单元包括两个具有相反导电类型的存储场效应晶体管，其栅极共同连接。单个写入晶体管连接在公共栅极和位线之间，用于从位线存储栅极上的电位。

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