会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Cycle segmented prefix circuits
    • 循环分割前缀电路
    • US06609189B1
    • 2003-08-19
    • US09267827
    • 1999-03-12
    • Bradley C. KuszmaulDana Sue Henry-Kuszmaul
    • Bradley C. KuszmaulDana Sue Henry-Kuszmaul
    • G06F9302
    • G06F7/506G06F9/3802G06F9/3836G06F9/3838G06F9/384G06F9/3844G06F9/3855G06F9/3857G06F9/3867G06F9/3869G06F9/3885G06F2207/5063
    • The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the window size. This patent presents a novel way to reimplement these components and reduce their critical-path delay growth. It then describes an entire processor microarchitecture, called the Ultrascalar processor, that has better critical-path delay growth than existing superscalars. Most of our scalable designs are based on a single circuit, a cyclic segmented parallel prefix (cspp). We observe that processor components typically operate on a wrap-around sequence of instructions, computing some associative property of that sequence. For example, to assign an ALU to the oldest requesting instruction, each instruction in the instruction sequence must be told whether any preceding instructions are requesting an ALU. Similarly, to read an argument register, an instruction must somehow communicate with the most recent preceding instruction that wrote that register. A cspp circuit can implement such functions by computing for each instruction within a wrap-around instruction sequence the accumulative result of applying some associative operator to all the preceding instructions. A cspp circuit has a critical path gate delay logarithmic in the length of the instruction sequence. Depending on its associative operation and its layout, a cspp circuit can have a critical path wire delay sublinear in the length of the instruction sequence.
    • 现有超标量处理器的可扩展性较差已成为计算机工程界极为关注的问题。 特别地,现有实现中的许多组件的关键路径延迟随着问题宽度和窗口大小而二次增长。 该专利提出了一种重新实现这些组件并减少其关键路径延迟增长的新方法。 然后,它描述了一种称为Ultrascalar处理器的整个处理器微架构,其具有比现有超标量更好的关键路径延迟增长。 我们的大部分可扩展设计都是基于单个电路,循环分段并行前缀(cspp)。 我们观察到,处理器组件通常在循环的指令序列上运行,计算该序列的一些关联属性。 例如,为了将ALU分配给最早的请求指令,必须告知指令序列中的每个指令是否有任何先前的指令要求ALU。 类似地,要读取参数寄存器,指令必须以某种方式与写入该寄存器的最新的前一条指令进行通信。 cspp电路可以通过对环绕指令序列内的每个指令计算将一些关联运算符应用于所有先前的指令的累积结果来实现这样的功能。 cspp电路在指令序列的长度上具有对数关键路径门延迟。 根据其关联操作及其布局,cspp电路可以在指令序列的长度上具有亚线性的关键路径线延迟。
    • 5. 发明授权
    • Method of routing a plurality of messages in a multi-node computer
network
    • 在多节点计算机网络中路由多个消息的方法
    • US5111198A
    • 1992-05-05
    • US629026
    • 1990-12-18
    • Bradley C. Kuszmaul
    • Bradley C. Kuszmaul
    • H04L12/56
    • H04L45/00H04L45/24
    • A message is generated at each of a plurality of source nodes, each message comprising at least address information identifying a first or destination node Di, and address information identifying a source node Si. The address information for the destination node is then used to route each message through the nodes of the communication network toward its destination node. At each node where two messages meet that are addressed to the same destination node, a second two messages are generated in place of the first two messages. One of these messages is routed toward the destination node while the other is routed toward an auxiliary node Ai whose address is specified in the message. If any further collisions take place between two messages routed to the same destination node, again two more messages are generated in place of the two colliding messages and one is routed toward the destination node while the other is routed toward another auxiliary node. The messages routed to the auxiliary node contain address information sufficient to route a message from the destination node to all the source nodes that originally addressed it.
    • 在多个源节点的每一个处生成消息,每个消息至少包括标识第一或目的节点Di的地址信息,以及标识源节点Si的地址信息。 然后,目的地节点的地址信息用于将通过通信网络的节点的每个消息路由到其目的地节点。 在两个消息满足的每个节点寻址到相同目的地节点的情况下,生成第二个两个消息来代替前两个消息。 这些消息之一被路由到目的地节点,而另一个消息被路由到在消息中指定其地址的辅助节点Ai。 如果在路由到同一目的地节点的两个消息之间发生任何进一步的冲突,则再次产生两个消息来代替两个冲突消息,一个路由到目的节点,而另一个被路由到另一个辅助节点。 路由到辅助节点的消息包含足以将消息从目的地节点路由到最初对其寻址的所有源节点的地址信息。
    • 10. 发明授权
    • Parallel computer system
    • 并行计算机系统
    • US5333268A
    • 1994-07-26
    • US946242
    • 1992-09-16
    • David C. DouglasMahesh N. GanmukhiJeffrey V. HillW. Daniel HillisBradley C. KuszmaulCharles E. LeisersonDavid S. WellsMonica C. WongShaw-Wen YangRobert C. Zak
    • David C. DouglasMahesh N. GanmukhiJeffrey V. HillW. Daniel HillisBradley C. KuszmaulCharles E. LeisersonDavid S. WellsMonica C. WongShaw-Wen YangRobert C. Zak
    • G06F15/16G06F11/00G06F11/08G06F11/22G06F15/173G06F15/80
    • G06F15/17381G06F11/08G06F11/22G06F11/324G06F15/17343H04L45/48H04L49/35H04L49/555G06F2201/88
    • A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.
    • 数字计算机包括多个处理元件,命令处理器,诊断处理器和通信网络。 处理元件各自执行与命令相关的数据处理和数据通信操作。 处理元件还响应诊断操作请求执行诊断操作,并响应于此提供诊断结果。 命令处理器为处理元件生成命令,并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。 诊断处理器产生诊断请求。 通信网络包括三个元件,包括数据路由器,控制网络和诊断网络。 数据路由器连接到处理元件,以便在数据通信操作期间便于它们之间的数据传输。 控制网络连接到处理元件和命令处理器,用于将命令从命令处理器传送到处理元件。 连接到处理元件的诊断网络,命令处理器和诊断处理器,用于将诊断请求从诊断处理器传送到处理元件和命令处理器,并将诊断结果从处理元件和命令处理器传送到诊断处理器。