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1. 发明授权

US09142768B2 Resistive memory with small electrode and method for fabricating the same 有权
标题翻译：具有小电极的电阻记忆及其制造方法
公开(公告)号：US09142768B2
公开(公告)日：2015-09-22
申请号：US13698799
申请日：2012-05-02
申请人： Yimao Cai , Jun Mao , Ru Huang , Shenghu Tan , Yinglong Huang , Yue Pan
发明人： Yimao Cai , Jun Mao , Ru Huang , Shenghu Tan , Yinglong Huang , Yue Pan
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625
摘要： Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.
摘要翻译：公开了涉及具有与ULSI中的半导体电阻性存储器的领域相关的具有小电极的电阻性存储器的系统和方法。示例性电阻存储器可以依次包括Al电极层，SiO 2层，Si层，电阻材料层和下电极层，其中Al电极层和电阻材料层通过一个或多个导电沟道电连接并且通过SiO 2层中的缺陷将Al材料穿过Si层而将Si材料溶解到Al材料中而形成导电通道。方法可以包括在衬底上形成下电极层，电阻层，Si层和SiO 2层; 在SiO 2层上制造Al电极层; 对所得到的结构进行退火处理。与本文的创新一致，可以通过常规方法获得小电极。

2. 发明授权

US08942036B2 Method for achieving four-bit storage using flash memory having splitting trench gate 有权
标题翻译：用于使用具有分裂沟槽栅极的闪存实现四位存储的方法
公开(公告)号：US08942036B2
公开(公告)日：2015-01-27
申请号：US13499596
申请日：2011-10-14
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
IPC分类号： G11C11/40 , H01L29/423 , G11C16/04 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42352 , G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.
摘要翻译：本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现一种编程模式。因此，提高了存储密度的装置的性能。

3. 发明申请

US20150021639A1 LIGHT EMITTING DIODE STRUCTURE 有权
标题翻译：发光二极管结构
公开(公告)号：US20150021639A1
公开(公告)日：2015-01-22
申请号：US14019553
申请日：2013-09-06
申请人： Yi-Ru Huang , Yu-Yun Lo , Chih-Ling Wu , Jing-En Huang , Shao-Ying Ting
发明人： Yi-Ru Huang , Yu-Yun Lo , Chih-Ling Wu , Jing-En Huang , Shao-Ying Ting
IPC分类号： H01L33/40
CPC分类号： H01L33/405 , H01L33/42
摘要： A light emitting diode structure including a substrate, a semiconductor epitaxial layer and a reflective conductive structure layer is provided. The semiconductor epitaxial layer is disposed on the substrate and exposes a portion of the substrate. The reflective conductive structure layer covers a part of the semiconductor epitaxial layer and the portion of the substrate exposed by the semiconductor epitaxial layer.
摘要翻译：提供了包括衬底，半导体外延层和反射导电结构层的发光二极管结构。半导体外延层设置在衬底上并暴露衬底的一部分。反射导电结构层覆盖半导体外延层的一部分和由半导体外延层曝光的基板的部分。

4. 发明授权

US08921174B2 Method for fabricating complementary tunneling field effect transistor based on standard CMOS IC process 有权
标题翻译：基于标准CMOS IC工艺制造互补隧道场效应晶体管的方法
公开(公告)号：US08921174B2
公开(公告)日：2014-12-30
申请号：US13884095
申请日：2012-06-14
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/739
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/823814 , H01L29/66356 , H01L29/7391
摘要： Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.
摘要翻译：本文公开了一种用于制造基于标准CMOS IC工艺的互补隧道场效应晶体管的方法，其属于超大规模集成（ULSI）电路中的场效应晶体管的逻辑器件和电路领域。在该方法中，TFET的本征通道和体区通过在标准CMOS IC工艺中的互补P阱和N阱掩模形成，以形成阱掺杂，沟道掺杂和通过注入进行阈值调整。此外，可以通过布局上的栅极和漏极之间的距离来抑制TFET中的双极效应，从而形成互补的TFET。在根据本发明的方法中，互补隧穿场效应晶体管（TFET）可以通过标准CMOS IC工艺中的现有工艺制造而无需任何附加的掩模和工艺步骤。

5. 发明授权

US08901644B2 Field effect transistor with a vertical channel and fabrication method thereof 有权
标题翻译：具有垂直沟道的场效应晶体管及其制造方法
公开(公告)号：US08901644B2
公开(公告)日：2014-12-02
申请号：US13821944
申请日：2011-09-09
申请人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
发明人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/04 , H01L29/775 , H01L29/06 , H01L21/28 , H01L29/41 , H01L29/423
CPC分类号： H01L29/7827 , B82Y10/00 , H01L21/2815 , H01L29/04 , H01L29/0653 , H01L29/0657 , H01L29/0676 , H01L29/0692 , H01L29/0847 , H01L29/413 , H01L29/42376 , H01L29/66439 , H01L29/66666 , H01L29/775
摘要： Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.
摘要翻译：本文公开了具有垂直沟道的场效应晶体管及其制造方法。场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口，在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

6. 发明授权

US08895980B2 Tunneling current amplification transistor 有权
标题翻译：隧道电流放大晶体管
公开(公告)号：US08895980B2
公开(公告)日：2014-11-25
申请号：US13255087
申请日：2011-05-26
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/73 , H01L29/739 , H01L29/00
CPC分类号： H01L29/7391
摘要： The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.
摘要翻译：本发明公开了一种隧道电流放大晶体管，其涉及CMOS超大规模半导体集成电路（ULSI）中的场效应晶体管逻辑器件的面积。隧道电流放大晶体管包括半导体衬底，栅极电介质层，发射极，漏极，浮动隧道基极和控制栅极，其中漏极，浮动隧道基极和控制栅极形成传统的TFET结构，以及发射极的掺杂类型与浮动隧道基体的掺杂类型相反。发射极的位置相对于漏极在浮动基底的另一侧。发射极和浮动隧道基底之间的半导体类型与浮动隧道基底的相同。与常规TFET相比，本发明的隧道电流放大晶体管可以有效地增加器件的导通电流，并提高器件的驱动能力。

7. 发明申请

US20140159082A1 LIGHT-EMITTING DEVICE 有权
标题翻译：发光装置
公开(公告)号：US20140159082A1
公开(公告)日：2014-06-12
申请号：US13917646
申请日：2013-06-14
申请人： Yi-Ru Huang , Jing-En Huang , Chih-Ling Wu , Yu-Yun Lo
发明人： Yi-Ru Huang , Jing-En Huang , Chih-Ling Wu , Yu-Yun Lo
IPC分类号： H01L33/22
CPC分类号： H01L33/22
摘要： A light-emitting device including a substrate, a photoelectric structure and a coarse structure is provided. The substrate has an upper surface and a lower surface opposite to each other, and an annular side surface connecting the upper surface and the lower surface. The photoelectric structure is disposed on the upper surface of the substrate. The coarse structure is formed on the annular side surface of the substrate. A ratio of a thickness of the substrate and a thickness of the coarse structure is greater than or equal to 1 and less than or equal to 20. Therefore, the overall light-emitting efficiency of the light-emitting device may be improved.
摘要翻译：提供了包括基板，光电结构和粗糙结构的发光器件。基板具有彼此相对的上表面和下表面，以及连接上表面和下表面的环形侧表面。光电结构设置在基板的上表面上。粗糙结构形成在基板的环形侧表面上。基板的厚度和粗糙结构的厚度的比例大于或等于1且小于或等于20.因此，可以提高发光器件的整体发光效率。

8. 发明授权

US08673722B2 Strained channel field effect transistor and the method for fabricating the same 有权
标题翻译：应变通道场效应晶体管及其制造方法
公开(公告)号：US08673722B2
公开(公告)日：2014-03-18
申请号：US13255443
申请日：2011-03-23
申请人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
发明人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L29/1083 , H01L29/66545 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/7849
摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.
摘要翻译：本发明公开了一种应变通道场效应晶体管及其制造方法。场效应晶体管包括衬底，源极/漏极，栅极电介质层和栅极，其特征在于，“L”形复合隔离层，其包围与源极/漏极相邻的侧面的一部分沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力。

9. 发明授权

US08592276B2 Fabrication method of vertical silicon nanowire field effect transistor 有权
标题翻译：垂直硅纳米线场效应晶体管的制造方法
公开(公告)号：US08592276B2
公开(公告)日：2013-11-26
申请号：US13501711
申请日：2011-11-18
申请人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
发明人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L29/66439 , H01L29/775
摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.
摘要翻译：本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力，并减少泄漏电流和漏极引起的屏障降低（DIBL）。另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

10. 发明授权

US08513639B2 Resistive-switching memory and fabrication method thereof 有权
标题翻译：电阻式开关存储器及其制造方法
公开(公告)号：US08513639B2
公开(公告)日：2013-08-20
申请号：US13254570
申请日：2011-04-12
申请人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
发明人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.
摘要翻译：本发明公开了一种电阻式开关存储器及其制造方法。电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部电极为板状。底部电极的峰值结构降低了器件的功耗。其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。整个制造工艺简单，可以实现高集成度的装置。

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