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1. 发明授权

US08942036B2 Method for achieving four-bit storage using flash memory having splitting trench gate 有权
标题翻译：用于使用具有分裂沟槽栅极的闪存实现四位存储的方法
公开(公告)号：US08942036B2
公开(公告)日：2015-01-27
申请号：US13499596
申请日：2011-10-14
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
IPC分类号： G11C11/40 , H01L29/423 , G11C16/04 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42352 , G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.
摘要翻译：本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现一种编程模式。因此，提高了存储密度的装置的性能。

2. 发明申请

US20120188821A1 METHOD FOR ACHIEVING FOUR-BIT STORAGE USING FLASH MEMORY HAVING SPLITTING TRENCH GATE 有权
标题翻译：使用具有分割式闸门的闪存存储器实现四位存储的方法
公开(公告)号：US20120188821A1
公开(公告)日：2012-07-26
申请号：US13499596
申请日：2011-10-14
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
IPC分类号： G11C16/34
CPC分类号： H01L29/42352 , G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.
摘要翻译：本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现一种编程模式。因此，提高了存储密度的装置的性能。

3. 发明申请

US20120261740A1 FLASH MEMORY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：闪存及其制造方法
公开(公告)号：US20120261740A1
公开(公告)日：2012-10-18
申请号：US13389720
申请日：2011-10-14
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Shenghu Tan
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Shenghu Tan
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7391 , H01L27/1203 , H01L29/788 , H01L29/8616
摘要： The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel. The method includes: 1) performing a shallow trench isolation on a SOI silicon substrate to form an active region; 2) sequentially forming a tunneling oxide layer and a first polysilicon layer on the SOI silicon substrate to form a polysilicon floating gate, and forming a blocking oxide layer and a second polysilicon layer to form a polysilicon control gate; 3) etching the resultant structure to form a gate stack structure; 4) forming a drain terminal at one side of the gate stack structure, etching the silicon film at the other side of the gate stack structure, growing a thin silicon nitride layer, and then refilling the hole structure with silicon material, to form a source terminal. The method has the advantages of high programming efficiency, low power consumption, effectively preventing source-drain punchthrough effect.
摘要翻译：本发明公开了一种闪速存储器及其制造方法，涉及半导体存储器的技术领域。闪速存储器包括掩埋氧层，其上设置有源极端子，沟道和漏极端子，其中沟道位于源极端子和漏极端子之间，以及隧道氧化物层，多晶硅浮动栅极，阻塞层氧化物层和多晶硅控制栅极依次设置在沟道上，并且在源极端子和沟道之间设置有薄的氮化硅层。该方法包括：1）在SOI硅衬底上进行浅沟槽隔离以形成有源区; 2）在SOI硅衬底上依次形成隧道氧化物层和第一多晶硅层，以形成多晶硅浮栅，并形成阻挡氧化层和第二多晶硅层以形成多晶硅控制栅极; 3）蚀刻所得结构以形成栅叠层结构; 4）在栅极堆叠结构的一侧形成漏极端子，蚀刻栅极叠层结构的另一侧的硅膜，生长薄的氮化硅层，然后用硅材料再填充孔结构，以形成源极终奌站。该方法具有编程效率高，功耗低，有效防止源极漏极穿通效应的优点。

4. 发明授权

US08526242B2 Flash memory and fabrication method and operation method for the same 有权
标题翻译：闪存及其制作方法及操作方法相同
公开(公告)号：US08526242B2
公开(公告)日：2013-09-03
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

5. 发明申请

US20120061637A1 3-D STRUCTURED NONVOLATILE MEMORY ARRAY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译： 3-D结构化非易失性存储器阵列及其制造方法
公开(公告)号：US20120061637A1
公开(公告)日：2012-03-15
申请号：US13131601
申请日：2011-04-01
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , LIjie Zhang , Yu Tang
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , LIjie Zhang , Yu Tang
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L27/0688 , H01L27/101 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/1691
摘要： The present invention relates to a field of nonvolatile memory technology in ULSI circuits manufacturing technology and discloses a 3D-structured resistive-switching memory array and a method for fabricating the same. The 3D-structured resistive-switching memory array according to the invention includes a substrate and a stack structure of bottom electrodes/isolation dielectric layers, deep trenches are etched in the stack structure of the bottom electrodes/the isolation dielectric layers; a resistive-switching material layer and a top electrode layer are deposited on sidewalls of the deep trenches, wherein the top electrodes and the bottom electrodes are crossed over each other on the sidewalls of the deep trenches with the resistive-switching material being interposed at cross-over points, each of the cross-over points forms one resistive-switching memory cell, and all of the resistive-switching memory cells form the 3D-structured resistive-switching memory array, and the 3D resistive-switching memory in the array are isolated by the isolation dielectric layers. According to the invention, the storage density of a resistive-switching memory can be improved, the process can be simplified, and the cost of the process can be reduced.
摘要翻译：本发明涉及ULSI电路制造技术中的非易失性存储器技术领域，并公开了一种3D结构的电阻式开关存储器阵列及其制造方法。根据本发明的3D结构的电阻式开关存储器阵列包括底部和底部电极/隔离电介质层的堆叠结构，在底部电极/隔离电介质层的堆叠结构中蚀刻深沟槽; 电阻切换材料层和顶部电极层沉积在深沟槽的侧壁上，其中顶部电极和底部电极在深沟槽的侧壁上彼此交叉，电阻切换材料插入在交叉通过点，每个交叉点形成一个电阻式开关存储单元，并且所有的电阻式开关存储单元形成三维结构的电阻式开关存储器阵列，阵列中的3D电阻式切换存储器是通过隔离绝缘层隔离。根据本发明，能够提高电阻式切换存储器的存储密度，能够简化处理，能够降低处理成本。

6. 发明申请

US20120113726A1 FLASH MEMORY AND FABRICATION METHOD AND OPERATION METHOD FOR THE SAME 有权
标题翻译：闪存及其制造方法和操作方法
公开(公告)号：US20120113726A1
公开(公告)日：2012-05-10
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C16/26 , H01L21/336 , H01L27/115
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

7. 发明授权

US08593848B2 Programming method for programming flash memory array structure 有权
标题翻译： Flash存储阵列结构编程方法
公开(公告)号：US08593848B2
公开(公告)日：2013-11-26
申请号：US13146005
申请日：2011-04-21
申请人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
发明人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
IPC分类号： G11C5/06
CPC分类号： G11C16/10 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.
摘要翻译：本发明提供一种闪存阵列结构及其编程方法，涉及超大规模集成电路制造技术中非易失性存储器的技术领域。本发明的闪速存储器阵列包括连接到存储单元的存储单元，字线和位线，其中连接到存储单元的控制栅极的字线和连接到存储单元的漏极端子的位线不垂直相互交叉但彼此成角度; 沿两个位线之间的通道方向彼此相邻的两个存储单元的控制栅极分别由两个字线控制，其漏极端分别由两个位线控制，并且其源极端子被共享。本发明还提供了一种用于编程闪存阵列结构的方法，其可以实现具有低功耗的编程。

8. 发明申请

US20120243313A1 SEMICONDUCTOR MEMORY ARRAY AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：半导体存储器阵列及其编程方法
公开(公告)号：US20120243313A1
公开(公告)日：2012-09-27
申请号：US13146005
申请日：2011-04-21
申请人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
发明人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.
摘要翻译：本发明提供一种闪存阵列结构及其编程方法，涉及超大规模集成电路制造技术中非易失性存储器的技术领域。本发明的闪速存储器阵列包括连接到存储单元的存储单元，字线和位线，其中连接到存储单元的控制栅极的字线和连接到存储单元的漏极端子的位线不垂直相互交叉但彼此成角度; 沿两个位线之间的通道方向彼此相邻的两个存储单元的控制栅极分别由两个字线控制，其漏极端分别由两个位线控制，并且其源极端子被共享。本发明还提供了一种用于编程闪存阵列结构的方法，其可以实现具有低功耗的编程。

9. 发明申请

US20120168770A1 HEAT DISSIPATION STRUCTURE OF CHIP 审中-公开
标题翻译：芯片散热结构
公开(公告)号：US20120168770A1
公开(公告)日：2012-07-05
申请号：US13391270
申请日：2011-11-18
申请人： Ru Huang , Xin Huang , Tianwei Zhang , Qianqian Huang , Shiqiang Qin
发明人： Ru Huang , Xin Huang , Tianwei Zhang , Qianqian Huang , Shiqiang Qin
IPC分类号： H01L29/20 , H01L29/12
CPC分类号： H01L23/38 , H01L23/3738 , H01L2924/0002 , H01L2924/00
摘要： A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.
摘要翻译：提供了微电子领域的芯片的散热结构。散热结构包括通过氧化隔离在芯片的上表面上形成的P型超晶格层和N型超晶格层。 P型超晶格和N型超晶格被氧化硅隔离。通过接触孔，P型超晶格与在芯片中施加低电位的金属层电连接，并且在P型超晶格上形成与外部电源连接的金属层。通过接触孔，N型超晶格电连接到在芯片中施加高电位电源的金属层，并且在N型超晶格上形成与外部电源连接的金属层。与P型超晶格连接的外部电源的电位低于与N型超晶格连接的外部电源的电位。本发明可以实现芯片的散热，同时通过使用超晶格具有低导热性和声子定位的特性的特征，同时防止环境热量转移到芯片中。

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