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1. 发明申请

US20120181584A1 Resistive Field Effect Transistor Having an Ultra-Steep Subthreshold Slope and Method for Fabricating the Same 审中-公开
标题翻译：具有超陡亚阈值斜率的电阻场效应晶体管及其制造方法
公开(公告)号：US20120181584A1
公开(公告)日：2012-07-19
申请号：US13318329
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/435
摘要： The invention discloses a resistive field effect transistor (ReFET) having an ultra-steep subthreshold slope, which relates to a field of field-effect-transistor logic device and circuit in CMOS ultra-large-scale-integrated circuit (ULSI). The resistive field effect transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a doped source region and a doped drain region, wherein the control gate is configured to adopt a stacked gate structure in which a bottom layer or a bottom electrode layer, a middle layer or a resistive material layer, and a top layer or a top electrode layer are sequentially formed. Compared with the existing methods for breaking the conventional subthreshold slope limititation, the device of the invention has a larger on-current, a lower operation voltage, and a better subthreshold feature.
摘要翻译：本发明公开了一种具有超陡亚阈值斜率的电阻场效应晶体管（ReFET），其涉及CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件和电路的场。电阻场效应晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，掺杂源极区域和掺杂漏极区域，其中控制栅极被配置为采用堆叠栅极结构，其中底层或顺序地形成底部电极层，中间层或电阻材料层，顶层或顶部电极层。与现有的破坏常规阈值斜率限制的方法相比，本发明的器件具有较大的导通电流，较低的工作电压和更好的亚阈值特性。

2. 发明授权

US08921174B2 Method for fabricating complementary tunneling field effect transistor based on standard CMOS IC process 有权
标题翻译：基于标准CMOS IC工艺制造互补隧道场效应晶体管的方法
公开(公告)号：US08921174B2
公开(公告)日：2014-12-30
申请号：US13884095
申请日：2012-06-14
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/739
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/823814 , H01L29/66356 , H01L29/7391
摘要： Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.
摘要翻译：本文公开了一种用于制造基于标准CMOS IC工艺的互补隧道场效应晶体管的方法，其属于超大规模集成（ULSI）电路中的场效应晶体管的逻辑器件和电路领域。在该方法中，TFET的本征通道和体区通过在标准CMOS IC工艺中的互补P阱和N阱掩模形成，以形成阱掺杂，沟道掺杂和通过注入进行阈值调整。此外，可以通过布局上的栅极和漏极之间的距离来抑制TFET中的双极效应，从而形成互补的TFET。在根据本发明的方法中，互补隧穿场效应晶体管（TFET）可以通过标准CMOS IC工艺中的现有工艺制造而无需任何附加的掩模和工艺步骤。

3. 发明授权

US08895980B2 Tunneling current amplification transistor 有权
标题翻译：隧道电流放大晶体管
公开(公告)号：US08895980B2
公开(公告)日：2014-11-25
申请号：US13255087
申请日：2011-05-26
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/73 , H01L29/739 , H01L29/00
CPC分类号： H01L29/7391
摘要： The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.
摘要翻译：本发明公开了一种隧道电流放大晶体管，其涉及CMOS超大规模半导体集成电路（ULSI）中的场效应晶体管逻辑器件的面积。隧道电流放大晶体管包括半导体衬底，栅极电介质层，发射极，漏极，浮动隧道基极和控制栅极，其中漏极，浮动隧道基极和控制栅极形成传统的TFET结构，以及发射极的掺杂类型与浮动隧道基体的掺杂类型相反。发射极的位置相对于漏极在浮动基底的另一侧。发射极和浮动隧道基底之间的半导体类型与浮动隧道基底的相同。与常规TFET相比，本发明的隧道电流放大晶体管可以有效地增加器件的导通电流，并提高器件的驱动能力。

4. 发明申请

US20120181585A1 Combined-source Mos Transistor with Comb-shaped Gate, and Method for Manufacturing the Same 有权
标题翻译：具有梳状门的组合源Mos晶体管及其制造方法
公开(公告)号：US20120181585A1
公开(公告)日：2012-07-19
申请号：US13318333
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/66643 , H01L29/7391 , H01L29/7839
摘要： The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same. The combined-source MOS transistor includes: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, wherein a Schottky source region is connected to a side of the highly-doped source region which is far from a channel, one end of the control gate extends to the highly-doped source region, the extended gate region is an extension gate in a form of a comb-shaped and the original control gate region is a main gate; an active region covered by the extension gate is also a channel region, and is a substrate material; the highly-doped source region which is formed by highly doping is located on both sides of each comb finger of the extension gate; and a Schottky junction is formed at a location where the Schottky source region and the channel under the extension gate are located. As compared with an existing MOSFET, in the invention, a higher turn-on current, a lower leakage current and a steeper subthreshold slope may be obtained under the same process condition and the same active region size.
摘要翻译：本发明公开了一种具有肖特基势垒和梳状栅极结构的组合源MOS晶体管及其制造方法。组合源MOS晶体管包括：控制栅极电极层，栅极电介质层，半导体衬底，高掺杂源极区域和高掺杂漏极区域，其中肖特基源极区域连接到高度远离通道的掺杂源极区域，控制栅极的一端延伸到高掺杂源极区域，延伸栅极区域是梳状形式的延伸栅极，并且原始控制栅极区域是大门; 由延伸栅极覆盖的有源区域也是沟道区域，并且是衬底材料; 通过高掺杂形成的高掺杂源区位于延伸门的每个梳齿的两侧; 并且在肖特基源区域和延伸门下方的沟道所在的位置处形成肖特基结。与现有的MOSFET相比，在本发明中，可以在相同的工艺条件和相同的有源区域尺寸下获得较高的导通电流，较低的漏电流和更陡的亚阈值斜率。

5. 发明申请

US20120313154A1 MOS Transistor Having Combined-Source Structure With Low Power Consumption and Method for Fabricating the Same 有权
标题翻译：具有低功耗的组合源结构的MOS晶体管及其制造方法
公开(公告)号：US20120313154A1
公开(公告)日：2012-12-13
申请号：US13501241
申请日：2011-10-14
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7839
摘要： The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.
摘要翻译：本发明公开了一种具有低功耗的组合源结构的MOS晶体管，其涉及CMOS超大规模集成电路中的场效应晶体管逻辑器件和电路领域。 MOS晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，肖特基源区，高掺杂源极区和高掺杂漏极区。控制栅极的一端延伸到高掺杂源极区域以形成T形，其中控制栅极的延伸区域是延伸栅极，控制栅极的其余区域是主栅极。由延伸栅极覆盖的有源区是沟道区，其材料是衬底材料。在肖特基源区域和延伸栅极下方的通道之间形成肖特基结。根据本发明的组合源结构组合了肖特基势垒和T形门，提高了器件的性能，其制造方法简单。因此，可以获得更高的导通电流，较低的漏电流和更陡的亚阈值斜率，并且本申请可以应用于低功耗领域并具有较高的实用价值。

6. 发明申请

US20120267700A1 TUNNELING CURRENT AMPLIFICATION TRANSISTOR 有权
标题翻译：隧道电流放大晶体管
公开(公告)号：US20120267700A1
公开(公告)日：2012-10-25
申请号：US13255087
申请日：2011-05-26
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/788
CPC分类号： H01L29/7391
摘要： The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.
摘要翻译：本发明公开了一种隧道电流放大晶体管，其涉及CMOS超大规模半导体集成电路（ULSI）中的场效应晶体管逻辑器件的面积。隧道电流放大晶体管包括半导体衬底，栅极电介质层，发射极，漏极，浮动隧道基极和控制栅极，其中漏极，浮动隧道基极和控制栅极形成传统的TFET结构，发射极的掺杂类型与浮动隧道基体的掺杂类型相反。发射极的位置相对于漏极在浮动基底的另一侧。发射极和浮动隧道基底之间的半导体类型与浮动隧道基底的相同。与常规TFET相比，本发明的隧道电流放大晶体管可以有效地增加器件的导通电流，并提高器件的驱动能力。

7. 发明授权

US08710557B2 MOS transistor having combined-source structure with low power consumption and method for fabricating the same 有权
标题翻译：具有低功耗的组合源结构的MOS晶体管及其制造方法
公开(公告)号：US08710557B2
公开(公告)日：2014-04-29
申请号：US13501241
申请日：2011-10-14
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Xin Huang , Yangyuan Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/7839
摘要： The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.
摘要翻译：本发明公开了一种具有低功耗的组合源结构的MOS晶体管，其涉及CMOS超大规模集成电路中的场效应晶体管逻辑器件和电路领域。 MOS晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，肖特基源区，高掺杂源极区和高掺杂漏极区。控制栅极的一端延伸到高掺杂源极区域以形成T形，其中控制栅极的延伸区域是延伸栅极，控制栅极的其余区域是主栅极。由延伸栅极覆盖的有源区是沟道区，其材料是衬底材料。在肖特基源区域和延伸栅极下方的通道之间形成肖特基结。根据本发明的组合源结构组合了肖特基势垒和T形门，提高了器件的性能，其制造方法简单。因此，可以获得更高的导通电流，较低的漏电流和更陡的亚阈值斜率，并且本申请可以应用于低功耗领域并具有较高的实用价值。

8. 发明授权

US08507959B2 Combined-source MOS transistor with comb-shaped gate, and method for manufacturing the same 有权
标题翻译：具有梳形门的组合源MOS晶体管及其制造方法
公开(公告)号：US08507959B2
公开(公告)日：2013-08-13
申请号：US13318333
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/76 , H01L21/00 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/66643 , H01L29/7391 , H01L29/7839
摘要： The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same. The combined-source MOS transistor includes: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, wherein a Schottky source region is connected to a side of the highly-doped source region which is far from a channel, one end of the control gate extends to the highly-doped source region, the extended gate region is an extension gate in a form of a comb-shaped and the original control gate region is a main gate; an active region covered by the extension gate is also a channel region, and is a substrate material; the highly-doped source region which is formed by highly doping is located on both sides of each comb finger of the extension gate; and a Schottky junction is formed at a location where the Schottky source region and the channel under the extension gate are located. As compared with an existing MOSFET, in the invention, a higher turn-on current, a lower leakage current and a steeper subthreshold slope may be obtained under the same process condition and the same active region size.
摘要翻译：本发明公开了一种具有肖特基势垒和梳状栅极结构的组合源MOS晶体管及其制造方法。组合源MOS晶体管包括：控制栅极电极层，栅极电介质层，半导体衬底，高掺杂源极区域和高掺杂漏极区域，其中肖特基源极区域连接到高度远离通道的掺杂源极区域，控制栅极的一端延伸到高掺杂源极区域，延伸栅极区域是梳状形式的延伸栅极，并且原始控制栅极区域是大门; 由延伸栅极覆盖的有源区域也是沟道区域，并且是衬底材料; 通过高掺杂形成的高掺杂源区位于延伸门的每个梳齿的两侧; 并且在肖特基源区域和延伸门下方的沟道所在的位置处形成肖特基结。与现有的MOSFET相比，在本发明中，在相同的工艺条件和相同的有源区域尺寸下可以获得较高的导通电流，较低的漏电流和更陡的亚阈值斜率。

9. 发明申请

US20120223361A1 LOW-POWER CONSUMPTION TUNNELING FIELD-EFFECT TRANSISTOR WITH FINGER-SHAPED GATE STRUCTURE 审中-公开
标题翻译：具有手指形状结构的低功耗消耗隧道场效应晶体管
公开(公告)号：US20120223361A1
公开(公告)日：2012-09-06
申请号：US13378920
申请日：2011-05-19
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/42312 , H01L29/66356
摘要： The present invention discloses a low-power consumption tunnelling field-effect transistor (TFET). The TFET according to the invention includes a source, a drain and a control gate, wherein the control gate extends towards the source to form a finger-type control gate, which includes an extended gate region and an original control gate region, and an active region covered by the extended gate region is also an channel region and is made of the substrate material. The invention employs a finger-shaped gate structure, and the source region of the TFET surrounds the channel so that the on-state current of the device is improved. In comparison with the conventional planar TFET, a higher on-state current and a steeper subthreshold slope may be obtained under the same process conditions and with the same active region size.
摘要翻译：本发明公开了一种低功耗隧道场效应晶体管（TFET）。根据本发明的TFET包括源极，漏极和控制栅极，其中控制栅极朝向源极延伸以形成指状型控制栅极，其包括扩展栅极区域和原始控制栅极区域，以及主动由扩展栅极区域覆盖的区域也是沟道区域并且由衬底材料制成。本发明采用指形栅极结构，并且TFET的源极区域围绕沟道，使得器件的导通电流得以改善。与传统的平面TFET相比，可以在相同的工艺条件和相同的有源区域尺寸下获得更高的导通电流和更陡的亚阈值斜率。

10. 发明申请

US20130214810A1 METHOD FOR TESTING DENSITY AND LOCATION OF GATE DIELECTRIC LAYER TRAP OF SEMICONDUCTOR DEVICE 有权
标题翻译：测试半导体器件栅极电介质层的密度和位置的方法
公开(公告)号：US20130214810A1
公开(公告)日：2013-08-22
申请号：US13879967
申请日：2012-02-28
申请人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
发明人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
IPC分类号： G01R31/26
CPC分类号： G01R31/2642 , G01R31/2621 , H01L22/14 , H01L22/34
摘要： Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.
摘要翻译：提出了一种用于测试半导体器件的栅介质层陷阱的密度和位置的方法。测试方法使用由泄漏路径产生的栅极泄漏电流来测试具有小面积（有效沟道面积小于0.5平方微米）的半导体器件的栅极介电层中的阱密度和二维陷阱位置。本发明特别适用于测试具有超小面积（有效通道面积小于0.05平方微米）的器件。在不同材料和不同工艺的情况下，本方法可以获得栅极电介质层的陷阱分布情况。在本方法中，器件要求简单，测试结构简单，测试成本低，测试快速，可在短时间内获得器件栅极电介质层的陷阱分布，适合用于大批量的自动测试，特别适用于超小型半导体器件制造过程中的过程监控和成品质量检测。

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