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    • 1. 发明授权
    • Congruent power and timing signals for device
    • 设备的一致功率和定时信号
    • US09099915B2
    • 2015-08-04
    • US13335762
    • 2011-12-22
    • Henry GeWelsin WangXing Zhang
    • Henry GeWelsin WangXing Zhang
    • G01R19/00H02M7/06G01R11/40G01R11/42H02M1/00
    • H02M7/06G01R11/40G01R11/42H02M7/068H02M2001/0064
    • Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.
    • 单个电子设备中的一致功率和定时信号。 在一个实施例中,电路可以仅包括一个可操作以产生功率信号和定时信号的隔离变压器。 在次级侧,两个分支可以提取功率信号和时钟信号,以在隔离次级侧的电路中使用。 第一分支可以耦合到变压器并且可操作以将信号操纵成诸如5V DC信号的功率信号。 类似地,第二电路支路可操作以将信号操纵成时钟信号,例如频率为1MHz的5V信号。 通过从次级侧的同一隔离变压器中提取电源信号和时钟信号,可以在集成电路设备上节省有价值的空间,只需要单个隔离变压器的绕组。
    • 2. 发明授权
    • Method for introducing channel stress and field effect transistor fabricated by the same
    • 引入沟道应力的方法和由其制造的场效应晶体管
    • US08450155B2
    • 2013-05-28
    • US13131602
    • 2011-04-01
    • Ru HuangQuanxin YunXia AnXing Zhang
    • Ru HuangQuanxin YunXia AnXing Zhang
    • H01L21/332H01L21/335H01L21/8232H01L21/336H01L21/8234
    • H01L29/7848H01L29/6653H01L29/66636H01L29/7833H01L29/7843
    • The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.
    • 本发明涉及CMOS超大规模集成电路,并且提供了一种引入沟道应力的方法和由其制造的场效应晶体管。 根据本发明,应变电介质层介于源极/漏极区域和场效应晶体管的衬底之间,并且通过直接接触衬底的应变介电层在沟道中诱发应变,从而改善 信道的载波移动性和设备的性能。 本发明的具体效果包括:通过使用具有拉伸应变的应变电介质层,可以在沟道中诱发拉伸应变,以增加通道的电子迁移率; 可以通过使用具有压缩应变的应变电介质层在沟道中诱发压缩应变,以增加通道的空穴迁移率。 根据本发明,不仅引入通道应力的有效性,而且基本上也提高了场效应晶体管的器件结构,从而增加了抑制器件的短沟道效应的能力。
    • 4. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    • 半导体器件及其制造方法
    • US20120187495A1
    • 2012-07-26
    • US13201618
    • 2010-09-25
    • Xia AnYue GuoQuanxin YunRu HuangXing Zhang
    • Xia AnYue GuoQuanxin YunRu HuangXing Zhang
    • H01L27/088H01L21/336
    • H01L21/26506H01L21/26513H01L21/823807H01L29/16H01L29/6659H01L29/7833H01L29/7848
    • The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.
    • 本发明提供了一种半导体器件及其制造方法,其中该方法包括:在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底,其中栅介电层 并且栅极电介质层上的栅极设置在有源区上,有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺,其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。 根据制造半导体器件的方法,通过硅杂质的注入,可以通过栅极和漏极区域中的晶格失配有效地将适当的应力引入锗通道中,使得沟道中电子的迁移率增强 并提高了设备​​的性能。
    • 8. 发明授权
    • Method and apparatus for merging images
    • 用于合并图像的方法和装置
    • US06522790B1
    • 2003-02-18
    • US09407188
    • 1999-09-28
    • Xing ZhangJian Zhang
    • Xing ZhangJian Zhang
    • G06K932
    • H04N1/3876G06T7/32G06T7/37
    • Two document images which have been compressed using the JBIG-2 standard for facsimile applications so as to include a plurality of index numbers, one or more positions in each image associated with the index numbers, and a group symbol for each index number can be merged to form a final composite image. Firstly, two virtual indexed images are formed by patterns of the index numbers at their associated positions in the document images. The patterns of index numbers in the two virtual indexed images are then compared (22) to determine whether there is correlation between the patterns of index numbers in at least parts of the two virtual indexed images. The two virtual indexed images are then merged (25), when there is a sufficient correlation, such that the parts that correlate overlap each other to provide a merged virtual indexed image, and then the index numbers in the merged virtual indexed image are replaced (7) by the corresponding group symbol to provide the final composite image.
    • 已经使用用于传真应用的JBIG-2标准压缩的两个文档图像可以被合并以包括多个索引号,与索引号相关联的每个图像中的一个或多个位置以及每个索引号的组符号 以形成最终的合成图像。 首先,通过在文档图像中的相关位置处的索引号的图案形成两个虚拟索引图像。 然后比较(22)两个虚拟索引图像中的索引号的模式,以确定在两个虚拟索引图像的至少部分中的索引号的模式之间是否存在相关性。 然后,当存在足够的相关性时,两个虚拟索引图像被合并(25),使得相关的部分彼此重叠以提供合并的虚拟索引图像,然后替换合并的虚拟索引图像中的索引号( 7)由相应的组符号提供最终的合成图像。
    • 10. 发明授权
    • Strained channel field effect transistor and the method for fabricating the same
    • 应变通道场效应晶体管及其制造方法
    • US08673722B2
    • 2014-03-18
    • US13255443
    • 2011-03-23
    • Ru HuangQuanxin YunXia AnYujie AlXing Zhang
    • Ru HuangQuanxin YunXia AnYujie AlXing Zhang
    • H01L21/336
    • H01L29/0653H01L29/1083H01L29/66545H01L29/66636H01L29/7833H01L29/7834H01L29/7848H01L29/7849
    • The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.
    • 本发明公开了一种应变通道场效应晶体管及其制造方法。 场效应晶体管包括衬底,源极/漏极,栅极电介质层和栅极,其特征在于,“L”形复合隔离层,其包围与源极/漏极相邻的侧面的一部分 沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层,即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。 这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率,同时从根本上改善了场效应晶体管的器件结构,提高了器件的短沟道效应抑制能力 。