专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06750673B1 Method for measuring an effective channel length of a MOSFET 有权
标题翻译：测量MOSFET有效沟道长度的方法
公开(公告)号：US06750673B1
公开(公告)日：2004-06-15
申请号：US10249443
申请日：2003-04-10
申请人： Heng-Sheng Huang , Gary Hong , Shih-Chieh Lin , Yueh-Hsun Lee
发明人： Heng-Sheng Huang , Gary Hong , Shih-Chieh Lin , Yueh-Hsun Lee
IPC分类号： G01R3126
CPC分类号： H01L22/12
摘要： A first compensation factor, a second compensation factor and a third compensation factor are provided to improve a capacitance-voltage (C-V) method for measuring an effective channel length of a metal-oxide-semiconductor field effect transistor (MOSFET), and an overlap length of a gate and a source and a drain of the transistor. The first compensation factor is calculated by measuring two unit length gate capacitances of the transistor. The second compensation factor is calculated by measuring two unit length overlap capacitances of the transistor. The third compensation factor is a ratio of the second compensation factor to the first compensation factor.
摘要翻译：提供第一补偿因子，第二补偿因子和第三补偿因子以改善用于测量金属氧化物半导体场效应晶体管（MOSFET）的有效沟道长度的电容电压（CV）方法，以及重叠长度的晶体管的栅极和源极和漏极。通过测量晶体管的两个单位长度栅极电容来计算第一个补偿因子。通过测量晶体管的两个单位长度重叠电容来计算第二个补偿因子。第三补偿因子是第二补偿因子与第一补偿因子的比率。

2. 发明授权

US6165913A Manufacturing method for spacer 失效
标题翻译：垫片的制造方法
公开(公告)号：US6165913A
公开(公告)日：2000-12-26
申请号：US957922
申请日：1997-10-27
申请人： Tony Lin , Heng-Sheng Huang
发明人： Tony Lin , Heng-Sheng Huang
IPC分类号： H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/308
CPC分类号： H01L29/6659 , H01L29/4983 , H01L29/6656
摘要： A method for manufacturing spacers comprising the steps of first providing a semiconductor substrate having a gate electrode already formed thereon, and then sequentially depositing oxide, silicon nitride and oxide over the gate electrode and the substrate to form a first oxide layer, a silicon nitride layer and a second oxide layer. Subsequently, the second oxide layer is etched to form an oxide spacer above the silicon nitride layer. Thereafter, using the oxide spacer as a mask, a dry etching method having a high etching selectivity ratio for silicon nitride/oxide is used to etch the silicon nitride layer to form a silicon nitride spacer. Finally, the oxide spacer is removed using an oxide dip method. The silicon nitride spacers of this invention can have a greater thickness, more thickness uniformity, and a higher reliability for hot carriers. In addition, the method used in the invention can have a better control over the thickness.
摘要翻译：一种用于制造间隔物的方法，包括以下步骤：首先提供其上已经形成有栅电极的半导体衬底，然后在栅电极和衬底上依次沉积氧化物，氮化硅和氧化物以形成第一氧化物层，氮化硅层和第二氧化物层。随后，蚀刻第二氧化物层以在氮化硅层上形成氧化物间隔物。此后，使用氧化物间隔物作为掩模，使用对于氮化硅/氧化物具有高蚀刻选择性比的干蚀刻方法来蚀刻氮化硅层以形成氮化硅间隔物。最后，使用氧化物浸渍法除去氧化物间隔物。本发明的氮化硅间隔物可以具有更大的厚度，更多的厚度均匀性和对热载体的更高的可靠性。此外，本发明中使用的方法可以更好地控制厚度。

3. 发明授权

US6153478A STI process for eliminating kink effect 失效
标题翻译：消除扭结效应的STI工艺
公开(公告)号：US6153478A
公开(公告)日：2000-11-28
申请号：US14755
申请日：1998-01-28
申请人： Tony Lin , Wen-Kuan Yeh , Heng-Sheng Huang
发明人： Tony Lin , Wen-Kuan Yeh , Heng-Sheng Huang
IPC分类号： H01L21/762 , H01L21/00
CPC分类号： H01L21/76235
摘要： The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the semiconductor substrate. Sidewall spacers are formed on the opening and a portion of the semiconductor substrate is removed to form a trench, through an aperture defined by the sidewall spacers. The sidewall spacers is then removed and a liner layer is formed conformably over the trench.
摘要翻译：该过程包括以下步骤。首先，在半导体衬底上形成掩模层。然后去除掩模层的一部分以形成到半导体衬底的开口。侧壁间隔件形成在开口上，并且半导体衬底的一部分被去除以形成通过由侧壁间隔件限定的孔的沟槽。然后去除侧壁间隔物，并且衬垫层顺应地形成在沟槽上。

4. 发明授权

US06064107A Gate structure of a semiconductor device having an air gap 失效
标题翻译：具有气隙的半导体器件的栅极结构
公开(公告)号：US06064107A
公开(公告)日：2000-05-16
申请号：US56276
申请日：1998-04-07
申请人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
发明人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/00
CPC分类号： H01L29/66583 , H01L29/4983 , H01L29/4991 , H01L29/42376 , H01L29/4238 , H01L29/665
摘要： A semiconductor device comprises a semiconductor substrate, a source/drain region formed in the substrate, a gate oxide layer on the substrate between the source/drain region, a conductive layer on the gate oxide layer, a spacer around a side wall of the gate, and an air gap between the gate and the spacer. The spacer is not directly connected with the gate. The air gap is formed between the gate and the spacer.
摘要翻译：半导体器件包括半导体衬底，形成在衬底中的源极/漏极区，源极/漏极区之间的衬底上的栅极氧化物层，栅极氧化物层上的导电层，栅极侧壁周围的间隔物，以及栅极和间隔物之间的气隙。间隔件不直接与门连接。气隙形成在栅极和间隔物之间。

5. 发明授权

US5989956A DRAM capacitor process 失效
标题翻译： DRAM电容器工艺
公开(公告)号：US5989956A
公开(公告)日：1999-11-23
申请号：US814377
申请日：1997-03-11
申请人： Heng-Sheng Huang
发明人： Heng-Sheng Huang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A DRAM capacitor is formed by providing an opening to the surface of the drain of a memory cell's pass transistor. A first layer of polysilicon is deposited over the device and in contact with the drain of the pass transistor. Arsenic ions are implanted into the first layer of polysilicon and the first layer of polysilicon is annealed. A second layer of polysilicon is deposited over the first. Phosphorus ions are implanted into the surface of the second layer of polysilicon. A mask is formed over the two polysilicon layers, and the two layers are etched to define the lateral extent of the memory cell capacitor's lower electrode. An etch that preferentially etches doped polysilicon is used to laterally etch the (doped and annealed) first polysilicon layer, thereby undercutting the second polysilicon layer. The second polysilicon layer is then annealed. A dielectric film is formed on the surface of the lower electrode and an upper electrode consisting of doped polysilicon is formed over the surface of the dielectric layer. Forming a DRAM capacitor in this manner prevents impurities implanted into the polysilicon lower electrode of the capacitor from diffusing into the substrate in a manner which could expand the size of the drain region.
摘要翻译：通过向存储单元的传输晶体管的漏极的表面提供开口来形成DRAM电容器。第一层多晶硅沉积在器件上并与传输晶体管的漏极接触。将砷离子注入到第一层多晶硅中，第一层多晶硅退火。第一层沉积第二层多晶硅。将磷离子注入第二层多晶硅的表面。在两个多晶硅层上形成掩模，蚀刻两层以限定存储单元电容器的下电极的横向范围。优选蚀刻掺杂多晶硅的蚀刻用于横向蚀刻（掺杂和退火）的第一多晶硅层，从而底切第二多晶硅层。然后将第二多晶硅层退火。在下电极的表面上形成电介质膜，在电介质层的表面上形成由掺杂多晶硅构成的上电极。以这种方式形成DRAM电容器可以防止注入到电容器的多晶硅下电极中的杂质以扩大漏极区的尺寸的方式扩散到衬底中。

6. 发明授权

US5918131A Method of manufacturing a shallow trench isolation structure 失效
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US5918131A
公开(公告)日：1999-06-29
申请号：US961062
申请日：1997-10-30
申请人： Shih-Ying Hsu , Heng-Sheng Huang
发明人： Shih-Ying Hsu , Heng-Sheng Huang
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76
CPC分类号： H01L21/76232
摘要： A method of manufacturing a shallow trench isolation structure that utilizes the early formation of a strong oxide spacers so that for any subsequent pad oxide layer or sacrificial oxide layer removal using a wet etching method, the oxide layer adjacent to the substrate will not be over-etched to form recesses, thereby preventing the lowering of threshold voltage and the induction of a kink effect. The method includes the steps of forming a mask over a substrate and then patterning the mask to form a protective layer for subsequent etching operation. An oxide space is farmed on the sidewalls of the mask over the surface of the substrate. Subsequently, a trench is formed in the substrate along the side edges of the oxide spacers. A liner oxide box is formed on the sidewall of the trend and the liner oxide layer does not fill the trench. This is followed by filling the trench with a second oxide layer. After planarizing the upper surface with a chemical-mechanical polishing action, the mask is removed.
摘要翻译：一种制造浅沟槽隔离结构的方法，其利用早期形成强氧化物间隔物，使得对于任何后续的衬垫氧化物层或使用湿蚀刻方法的牺牲氧化物层去除，与衬底相邻的氧化物层将不会过量，蚀刻形成凹部，从而防止阈值电压的降低和扭结效应的诱导。该方法包括以下步骤：在衬底上形成掩模，然后对掩模进行图案化以形成用于后续蚀刻操作的保护层。掩模的侧壁上的氧化物空间被堆积在衬底的表面上。随后，沿着氧化物间隔物的侧边缘在衬底中形成沟槽。在趋势的侧壁上形成衬里氧化物盒，并且衬垫氧化物层不填充沟槽。然后用第二氧化物层填充沟槽。在用化学机械抛光作用对上表面进行平面化之后，去除掩模。

7. 发明授权

US5684417A Data sensing apparatus of a read only memory device 失效
标题翻译：只读存储器件的数据感测装置
公开(公告)号：US5684417A
公开(公告)日：1997-11-04
申请号：US555715
申请日：1995-11-14
申请人： Heng-Sheng Huang , Kun-Luh Chen
发明人： Heng-Sheng Huang , Kun-Luh Chen
IPC分类号： G11C7/06 , G01R19/00
CPC分类号： G11C7/067
摘要： A data sensing apparatus particularly useful for sensing a ROM device. The apparatus can be used with various voltage level devices because it has an adjustable load. A first load element is connected to the voltage source applied to the ROM device. A second load element is connected in parallel with the first load element. A switching element is connected to the first load element and provides a path for a sensing current of the ROM device. An inverter, responsive to the sensing current, controls the switching element. An amplifier, connected to the switching element, provides a useful output indicative of the sensing current of the ROM device. A voltage level detector detects the voltage level of the voltage source. It disables the second load element so as to increase the load when the voltage level of the voltage source is higher than a predetermined value.
摘要翻译：一种特别适用于感测ROM装置的数据感测装置。该装置可以与各种电压电平装置一起使用，因为它具有可调整的负载。第一负载元件连接到施加到ROM器件的电压源。第二负载元件与第一负载元件并联连接。开关元件连接到第一负载元件并提供用于ROM器件的感测电流的路径。响应于感测电流的逆变器控制开关元件。连接到开关元件的放大器提供指示ROM器件的感测电流的有用输出。电压电平检测器检测电压源的电压电平。它禁止第二负载元件，以便当电压源的电压电平高于预定值时增加负载。

8. 发明授权

US6057208A Method of forming shallow trench isolation 失效
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US6057208A
公开(公告)日：2000-05-02
申请号：US057905
申请日：1998-04-09
申请人： Tony Lin , Heng-Sheng Huang
发明人： Tony Lin , Heng-Sheng Huang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation structure is disclosed. A dielectric layer deposited by chemical vapor deposition is used as a sacrificial layer instead of conventional sacrificial oxide layer formed by thermal oxidation. Therefore, the oxide in the trench is further protected and less damaged.
摘要翻译：公开了形成浅沟槽隔离结构的方法。通过化学气相沉积沉积的电介质层用作牺牲层，而不是通过热氧化形成的常规牺牲氧化物层。因此，沟槽中的氧化物被进一步保护并且损坏较少。

9. 发明授权

US6043545A MOSFET device with two spacers 失效
标题翻译：具有两个间隔器的MOSFET器件
公开(公告)号：US6043545A
公开(公告)日：2000-03-28
申请号：US116533
申请日：1998-07-16
申请人： H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
发明人： H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/76
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S257/90
摘要： A MOSFET device protects the device from the short channel effect and decrease the resistance of a gate of the device. The MOSFET device includes a gate formed on a substrate and two source/drain regions. The source/drain regions are formed in the substrate at the sides of the gate. An oxide layer includes a first structure and a second structure. The first structure is at the side walls of the gate with the top of the first structure being lower than the top of the gate. The second structure is formed on the substrate and is connected to the first structure. A first spacer is formed on the second structure and beside the first structure. A second spacer is formed on the second structure and beside the first spacer. A self-aligned metal layer is formed on the gate, the first spacer, and over the substrate. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.
摘要翻译： MOSFET器件保护器件免受短沟道效应的影响，并降低器件栅极的电阻。 MOSFET器件包括形成在衬底上的栅极和两个源极/漏极区域。源极/漏极区域形成在栅极侧面的衬底中。氧化物层包括第一结构和第二结构。第一结构在栅极的侧壁处，第一结构的顶部低于栅极的顶部。第二结构形成在基板上并连接到第一结构。第一间隔件形成在第二结构上并且在第一结构的旁边。第二间隔件形成在第二结构上并且在第一间隔件的旁边。在栅极，第一间隔物和衬底上形成自对准金属层。结果，MOSFET器件在第一间隔物下方具有超浅结，以减少源/漏电阻并增加器件的工作速率。

10. 发明授权

US6004632A Method for increasing etch removal rate of silicon oxynitride 失效
标题翻译：提高氮氧化硅蚀刻去除率的方法
公开(公告)号：US6004632A
公开(公告)日：1999-12-21
申请号：US992674
申请日：1997-12-17
申请人： Shih-Ying Hsu , Chih-Hsiang Hsiao , Heng-Sheng Huang
发明人： Shih-Ying Hsu , Chih-Hsiang Hsiao , Heng-Sheng Huang
IPC分类号： C23C16/30 , H01L21/311 , H05H1/24
CPC分类号： C23C16/308 , H01L21/31116
摘要： A method for depositing a silicon oxynitride layer that has a higher etch-removal rate. The deposition starts by first passing gas from a pipeline A into the deposition chamber before switching the RF power source on. The further is the delay in switching the RF power source on, the higher will be the etch-removal rate of the silicon oxynitride layer formed by the deposition. Furthermore, the RF power source will remain on for a short period after the pump starts pumping gas away from the deposition chamber through pipeline A at the end of the deposition. The sooner is the switching off of the RB power source after the pump start to operate, the higher will be the etch-removal rate of the silicon oxynitride layer that result from the deposition.
摘要翻译：一种沉积具有较高蚀刻去除速率的氮氧化硅层的方法。沉积开始于在将RF电源接通之前首先将气体从管线A通入沉积室。进一步是切换RF电源的延迟，通过沉积形成的氧氮化硅层的蚀刻去除率越高。此外，在沉积结束后，泵通过管道A从沉积室泵送气体之后，RF电源将保持打开一段短时间。在泵开始运行之后，RB电源的关闭越早，沉积产生的氮氧化硅层的蚀刻去除率越高。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式