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1. 发明授权

US6015746A Method of fabricating semiconductor device with a gate-side air-gap structure 失效
标题翻译：制造具有栅极侧气隙结构的半导体器件的方法
公开(公告)号：US6015746A
公开(公告)日：2000-01-18
申请号：US056530
申请日：1998-04-07
申请人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
发明人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66583 , H01L29/4983 , H01L29/4991 , H01L29/42376 , H01L29/4238 , H01L29/665
摘要： A method of fabricating a semiconductor device. On a semiconductor substrate comprising a device isolation structure and an active region isolated by the device isolation region, an oxide layer is formed and etched on the active region to form an opening, so that the active within the opening is exposed. A first spacer is formed on a side wall of the opening. A gate oxide layer is formed on the active region within the opening. A conductive layer is formed on the gate oxide layer, so that the opening is filled thereby. The oxide layer is removed. The exposed active region is lightly doped to form a lightly doped region by using the conductive layer and the first spacer as a mask. A second spacer is formed on a side wall of the first spacer and leaves a portion of the first spacer to be exposed. The exposed active region is heavily doped to form a source/drain region by using the conductive layer, the first spacer, and the second spacer as a mask. The first spacer is removed to define a gate, so that an air gap between the gate and the second spacer is formed.
摘要翻译：一种制造半导体器件的方法。在包括器件隔离结构和由器件隔离区隔离的有源区的半导体衬底上，在有源区上形成氧化层并蚀刻以形成开口，从而露出开口内的活性物质。第一间隔件形成在开口的侧壁上。栅极氧化层形成在开口内的有源区上。在栅极氧化物层上形成导电层，从而填充开口。去除氧化物层。通过使用导电层和第一间隔物作为掩模，暴露的有源区域被轻掺杂以形成轻掺杂区域。第二间隔件形成在第一间隔件的侧壁上并且留下待暴露的第一间隔件的一部分。通过使用导电层，第一间隔件和第二间隔件作为掩模，暴露的有源区域被重掺杂以形成源极/漏极区域。去除第一间隔物以限定栅极，从而形成栅极和第二间隔物之间的气隙。

2. 发明授权

US6153478A STI process for eliminating kink effect 失效
标题翻译：消除扭结效应的STI工艺
公开(公告)号：US6153478A
公开(公告)日：2000-11-28
申请号：US14755
申请日：1998-01-28
申请人： Tony Lin , Wen-Kuan Yeh , Heng-Sheng Huang
发明人： Tony Lin , Wen-Kuan Yeh , Heng-Sheng Huang
IPC分类号： H01L21/762 , H01L21/00
CPC分类号： H01L21/76235
摘要： The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the semiconductor substrate. Sidewall spacers are formed on the opening and a portion of the semiconductor substrate is removed to form a trench, through an aperture defined by the sidewall spacers. The sidewall spacers is then removed and a liner layer is formed conformably over the trench.
摘要翻译：该过程包括以下步骤。首先，在半导体衬底上形成掩模层。然后去除掩模层的一部分以形成到半导体衬底的开口。侧壁间隔件形成在开口上，并且半导体衬底的一部分被去除以形成通过由侧壁间隔件限定的孔的沟槽。然后去除侧壁间隔物，并且衬垫层顺应地形成在沟槽上。

3. 发明授权

US06064107A Gate structure of a semiconductor device having an air gap 失效
标题翻译：具有气隙的半导体器件的栅极结构
公开(公告)号：US06064107A
公开(公告)日：2000-05-16
申请号：US56276
申请日：1998-04-07
申请人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
发明人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/00
CPC分类号： H01L29/66583 , H01L29/4983 , H01L29/4991 , H01L29/42376 , H01L29/4238 , H01L29/665
摘要： A semiconductor device comprises a semiconductor substrate, a source/drain region formed in the substrate, a gate oxide layer on the substrate between the source/drain region, a conductive layer on the gate oxide layer, a spacer around a side wall of the gate, and an air gap between the gate and the spacer. The spacer is not directly connected with the gate. The air gap is formed between the gate and the spacer.
摘要翻译：半导体器件包括半导体衬底，形成在衬底中的源极/漏极区，源极/漏极区之间的衬底上的栅极氧化物层，栅极氧化物层上的导电层，栅极侧壁周围的间隔物，以及栅极和间隔物之间的气隙。间隔件不直接与门连接。气隙形成在栅极和间隔物之间。

4. 发明授权

US06008118A Method of fabricating a barrier layer 失效
标题翻译：制造阻挡层的方法
公开(公告)号：US06008118A
公开(公告)日：1999-12-28
申请号：US59310
申请日：1998-04-13
申请人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
发明人： Wen-Kuan Yeh , Tony Lin , Heng-Sheng Huang
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76814 , H01L21/76826 , H01L21/76849 , H01L21/76867
摘要： A method of forming a barrier layer is disclosed. The barrier layer is formed on the upper surface of the tungsten plug. The method of forming the barrier layer is mainly a nitridation reaction. The nitridation reaction makes use of NH.sub.3 plasma, N.sub.2 plasma and N.sup.+ implantation.
摘要翻译：公开了形成阻挡层的方法。阻挡层形成在钨丝塞的上表面上。形成阻挡层的方法主要是氮化反应。氮化反应使用NH3等离子体，N2等离子体和N +注入。

5. 发明授权

US06197642B1 Method for manufacturing gate terminal 失效
标题翻译：栅极端子制造方法
公开(公告)号：US06197642B1
公开(公告)日：2001-03-06
申请号：US09028521
申请日：1998-02-24
申请人： Wen-Kuan Yeh , Heng-Sheng Huang
发明人： Wen-Kuan Yeh , Heng-Sheng Huang
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/28079 , H01L29/495
摘要： A method for manufacturing a gate terminal comprising the steps of providing a substrate, then forming and patterning an oxide layer to form a gate region. Next, a gate oxide layer and a crystalline silicon layer are formed in the gate region. This is followed by depositing a tungsten layer in the gate region, and then polishing the tungsten layer to form a final tungsten layer functioning as the gate electrode. Finally, the oxide layer is removed. The method of this invention is able to control the dimensions of the gate terminal produced. Moreover, the formation of a thin crystalline silicon layer over the gate oxide layer helps to increase the bonding strength with the metallic layer, and that the gate electrode can be formed at a lower processing temperature. Therefore, the gate so formed has a higher quality and the processing of the semiconductor is much easier. Furthermore, the silicon nitride layer can serve as an etching stop layer during the etching operation of the oxide layer. Consequently, over-exposing the upper trench corner locations of a shallow trench isolation structure can be prevented, thereby avoiding current leakage problems.
摘要翻译：一种用于制造栅极端子的方法，包括以下步骤：提供衬底，然后形成和图案化氧化物层以形成栅极区域。接下来，在栅极区域形成栅氧化层和晶体硅层。然后在栅极区域中沉积钨层，然后抛光钨层以形成用作栅电极的最终钨层。最后，去除氧化物层。本发明的方法能够控制所制造的栅极端子的尺寸。此外，在栅极氧化物层上形成薄的晶体硅层有助于增加与金属层的结合强度，并且可以在较低的处理温度下形成栅电极。因此，如此形成的栅极具有更高的质量，并且半导体的处理容易得多。此外，在氧化物层的蚀刻操作期间，氮化硅层可以用作蚀刻停止层。因此，可以防止浅沟槽隔离结构的上沟槽角部位的过度曝光，从而避免电流泄漏问题。

6. 发明授权

US06200870B1 Method for forming gate 有权
标题翻译：浇口形成方法
公开(公告)号：US06200870B1
公开(公告)日：2001-03-13
申请号：US09189355
申请日：1998-11-09
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28061 , H01L21/28247
摘要： A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.
摘要翻译：用于形成提高栅极质量的栅极的方法包括在衬底上顺序地形成栅极氧化物层，多晶硅层，导电层和掩模层。此后，对掩模层，导电层，多晶硅层和栅极氧化物层进行图案化以形成栅极。然后，通过用氮阳离子的离子注入，在导电层的侧壁上形成用于增加栅极的热稳定性和化学稳定性的钝化层。氮阳离子通过离子注入在栅极氧化物层下方掺杂到衬底中，这可以改善磷离子的渗透。

7. 发明授权

US06165857A Method for forming a transistor with selective epitaxial growth film 有权
标题翻译：用选择性外延生长膜形成晶体管的方法
公开(公告)号：US06165857A
公开(公告)日：2000-12-26
申请号：US469008
申请日：1999-12-21
申请人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
发明人： Wen-Kuan Yeh , Tony Lin , Jih-Wen Chou
IPC分类号： H01L21/28 , H01L21/336 , H01L29/417
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/41775 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer. Next, the first dielectric layer is etched until upper surface of the gate and a portion of the substrate are exposed, wherein a part of the second dielectric layer is also etched accompanying with etching a part of the first dielectric layer. Further, second ions are implanted into the exposed substrate to form a source/drain region. A conductive layer is selectively formed on said over the exposed gate and source/drain. Finally, a self-aligned silicide layer is formed over the conductive layer.
摘要翻译：公开了选择性外延生长的新改进。在一个实施例中，本发明提供一种包括衬底的低功率金属氧化物半导体场效应晶体管（MOSFET）。接着，在基板上形成栅极氧化层。此外，在栅极氧化物层上沉积多晶硅层。图案化以蚀刻多晶硅层和栅极氧化物层以限定栅极。通过使用所述栅极作为硬掩模将第一离子注入到衬底中。接下来，衬垫氧化物覆盖在所得结构的整个暴露表面上。此外，适形的第一介电层和第二介电层以适当的顺序沉积在衬垫氧化物的上方。回蚀第二电介质层以在第一电介质层的侧壁上形成电介质间隔物。接下来，蚀刻第一电介质层直到栅极的上表面和衬底的一部分被暴露，其中第二电介质层的一部分也被蚀刻，同时蚀刻第一介电层的一部分。此外，将第二离子注入暴露的衬底中以形成源/漏区。在暴露的栅极和源极/漏极上的选择性地形成导电层。最后，在导电层上形成自对准的硅化物层。

8. 发明授权

US6153483A Method for manufacturing MOS device 失效
标题翻译：制造MOS器件的方法
公开(公告)号：US6153483A
公开(公告)日：2000-11-28
申请号：US193005
申请日：1998-11-16
申请人： Wen-Kuan Yeh , Tony Lin
发明人： Wen-Kuan Yeh , Tony Lin
IPC分类号： H01L21/266 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/4983 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing MOS device that utilizes a special shape spacer as a mask in an ion implantation operation to form a graded source/drain region. The special shaped spacer has a thin wall section on the far side away from the gate so that as ions are implanted into the substrate to form a source/drain region, dopants are implanted to various depths. The graded doping profile in the source/drain region not only reduces the severity of short channel effects, but also forms a base for forming an integral junction over the source/drain region in subsequent self-aligned silicide process.
摘要翻译：一种用于制造在离子注入操作中利用特殊形状间隔物作为掩模的MOS器件的方法，以形成渐变的源极/漏极区域。特殊形状的间隔件在远离栅极的远侧具有薄壁部分，使得当离子注入到衬底中以形成源极/漏极区域时，掺杂剂被植入各种深度。源极/漏极区域中的渐变掺杂分布不仅降低了短沟道效应的严重性，而且还形成了在随后的自对准硅化物工艺中在源极/漏极区域上形成整体结的基极。

9. 发明授权

US6022785A Method of fabricating a metal-oxide-semiconductor transistor 失效
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US6022785A
公开(公告)日：2000-02-08
申请号：US126462
申请日：1998-07-30
申请人： Wen-Kuan Yeh , Tony Lin
发明人： Wen-Kuan Yeh , Tony Lin
IPC分类号： H01L21/336 , H01L29/10 , H01L21/425
CPC分类号： H01L29/6659 , H01L29/1083
摘要： The invention discloses a method of forming a metal-oxide-semiconductor transistor. The method provides a substrate, where a gate structure is formed thereon. Next, a first spacer is formed on the sidewall of the gate structure. A pair of heavily doped regions is formed in the substrate. Then, an annealing process is performed to make the doped ions in the heavily doped regions uniformly distributed. Next, the first spacer is removed and a thin pad dielectric layer is formed over the substrate. Next, a first type halo structure is formed in the bottom portion of the source/drain region beneath the gate structure. A lightly doped region is formed between the gate structure and the first type halo structure and above the first type halo structure. An etching process is performed on the pad dielectric layer to form a second spacer and then the MOS transitor is completed.
摘要翻译：本发明公开了一种形成金属氧化物半导体晶体管的方法。该方法提供了其上形成栅极结构的衬底。接下来，在栅极结构的侧壁上形成第一间隔物。在衬底中形成一对重掺杂区域。然后，进行退火处理以使重掺杂区域中的掺杂离子均匀分布。接下来，去除第一间隔物，并在衬底上形成薄的衬垫介电层。接下来，在栅极结构下面的源极/漏极区域的底部形成第一类型的晕结构。在栅极结构和第一类型卤素结构之间并且在第一类型的晕结构之上形成轻掺杂区。在焊盘电介质层上进行蚀刻处理以形成第二间隔物，然后完成MOS过渡电极。

10. 发明授权

US6083827A Method for fabricating local interconnect 失效
标题翻译：制造局部互连的方法
公开(公告)号：US6083827A
公开(公告)日：2000-07-04
申请号：US212084
申请日：1998-12-15
申请人： Tony Lin , Coming Chen , Wen-Kuan Yeh
发明人： Tony Lin , Coming Chen , Wen-Kuan Yeh
IPC分类号： H01L21/321 , H01L21/336 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895 , H01L21/3212 , H01L29/66545
摘要： A method for fabricating a local interconnect. A gate having a gate oxide layer, a gate polysilicon layer and a cap layer is formed on a provided substrate. A spacer is formed on the sidewall of the gate, and a source/drain region is formed in the substrate. A planarized dielectric layer is formed over the substrate to expose the cap layer. A portion of the dielectric layer and the spacer on one side of the gate is removed to form an opening, so that the source/drain region is exposed. The opening is transformed into a local-interconnect opening by removing the cap layer. A local interconnect is formed by forming a conductive layer in the local-interconnect opening.
摘要翻译：一种用于制造局部互连的方法。在所提供的衬底上形成具有栅极氧化物层，栅极多晶硅层和覆盖层的栅极。在栅极的侧壁上形成间隔物，在衬底中形成源/漏区。平坦化介电层形成在衬底上以露出盖层。电介质层的一部分和栅极一侧上的间隔物被去除以形成开口，从而暴露出源极/漏极区域。通过去除盖层将开口转变成局部互连开口。通过在局部互连开口中形成导电层形成局部互连。

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