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1. 发明授权

US5920783A Method of fabricating a self-aligned silicide MOSFET 失效
标题翻译：制造自对准硅化物MOSFET的方法
公开(公告)号：US5920783A
公开(公告)日：1999-07-06
申请号：US55692
申请日：1998-04-06
申请人： H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
发明人： H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S257/90
摘要： A method of fabricating a MOSFET device in accordance with the present invention can protect the device from the short channel effect and decrease the resistance of a gate of the device. The fabricating method includes the following steps. A device including a substrate, an oxide layer, a gate and a lightly doped region is provided, wherein the oxide layer is formed on the substrate and the gate is formed on the oxide layer. A conducting layer is formed on the oxide layer, and the conducting layer is etched to form a first spacer. Then, the device is implanted to form a heavily doped region. A dielectric layer is deposited on the device, and the dielectric layer is etched to form a second spacer. The oxide layer is etched to expose part of the side walls of the gate. Then, a self-aligned silicide is further processed to complete the fabricating processes. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.
摘要翻译：根据本发明的制造MOSFET器件的方法可以保护器件免于短沟道效应并降低器件栅极的电阻。制造方法包括以下步骤。提供了包括衬底，氧化物层，栅极和轻掺杂区域的器件，其中氧化物层形成在衬底上，并且栅极形成在氧化物层上。在氧化物层上形成导电层，蚀刻导电层以形成第一间隔物。然后，将器件植入以形成重掺杂区域。在器件上沉积介电层，蚀刻电介质层以形成第二间隔物。蚀刻氧化物层以暴露栅极的一部分侧壁。然后，进一步处理自对准的硅化物以完成制造工艺。结果，MOSFET器件在第一间隔物下方具有超浅结，以减少源/漏电阻并增加器件的工作速率。

2. 发明授权

US6043545A MOSFET device with two spacers 失效
标题翻译：具有两个间隔器的MOSFET器件
公开(公告)号：US6043545A
公开(公告)日：2000-03-28
申请号：US116533
申请日：1998-07-16
申请人： H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
发明人： H. C. Tseng , Kun-Cho Chen , Heng-Sheng Huang
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/76
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659 , Y10S257/90
摘要： A MOSFET device protects the device from the short channel effect and decrease the resistance of a gate of the device. The MOSFET device includes a gate formed on a substrate and two source/drain regions. The source/drain regions are formed in the substrate at the sides of the gate. An oxide layer includes a first structure and a second structure. The first structure is at the side walls of the gate with the top of the first structure being lower than the top of the gate. The second structure is formed on the substrate and is connected to the first structure. A first spacer is formed on the second structure and beside the first structure. A second spacer is formed on the second structure and beside the first spacer. A self-aligned metal layer is formed on the gate, the first spacer, and over the substrate. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.
摘要翻译： MOSFET器件保护器件免受短沟道效应的影响，并降低器件栅极的电阻。 MOSFET器件包括形成在衬底上的栅极和两个源极/漏极区域。源极/漏极区域形成在栅极侧面的衬底中。氧化物层包括第一结构和第二结构。第一结构在栅极的侧壁处，第一结构的顶部低于栅极的顶部。第二结构形成在基板上并连接到第一结构。第一间隔件形成在第二结构上并且在第一结构的旁边。第二间隔件形成在第二结构上并且在第一间隔件的旁边。在栅极，第一间隔物和衬底上形成自对准金属层。结果，MOSFET器件在第一间隔物下方具有超浅结，以减少源/漏电阻并增加器件的工作速率。

3. 发明授权

US6110827A Planarization method for self-aligned contact process 失效
标题翻译：自对准接触过程的平面化方法
公开(公告)号：US6110827A
公开(公告)日：2000-08-29
申请号：US655074
申请日：1996-06-03
申请人： Sun-Chieh Chien , Der-Yuan Wu , Kun-Cho Chen
发明人： Sun-Chieh Chien , Der-Yuan Wu , Kun-Cho Chen
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76819 , Y10S438/959
摘要： A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.
摘要翻译：用于自对准接触工艺的平面化方法，适用于DRAM处理。在形成电容器的底部端子层之前，首先将衬底表面平坦化，从而在随后蚀刻限定的图案期间避免由起伏的表面轮廓引起的纵梁效应和相关的桥接问题。此外，根据本发明的方法，首先通过覆盖首先沉积氧化物层的MOS晶体管的硅衬底，然后蚀刻鉴别层，最后是平坦化层，具有平滑的平面表面的衬底获得。

4. 发明授权

US6025277A Method and structure for preventing bonding pad peel back 失效
标题翻译：防止粘结垫剥离的方法和结构
公开(公告)号：US6025277A
公开(公告)日：2000-02-15
申请号：US58959
申请日：1998-04-13
申请人： Kun-Cho Chen , Jason Jenq
发明人： Kun-Cho Chen , Jason Jenq
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L23/485 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/76804 , H01L21/76816 , H01L24/02 , H01L24/11 , H01L2224/0401 , H01L2224/13099 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/14 , H01L2924/15787
摘要： Bonding pad structures may be fabricated by forming a layered structure including a first conducting layer and first and second insulating layers on top of a substrate. Openings are etched through the first and second insulating layers, with the openings being wider in the first insulating layer than in the second insulating layer. The etching process may be carried out in two steps, with the second step preferentially isotropically etching the first insulating layer so that the openings are wider in the first insulating layer than in the second insulating layer and a portion of the second insulating layer overhangs the opening above the first insulating layer. Metal is then deposited within the openings and on top of the second insulating layer. An interlocking structure is formed with the conducting material extending underneath of the overhang portions of the second insulating layer. A passivation layer may be formed over the conducting material. The conducting material may include a barrier layer, a plug, and a top bond pad layer.
摘要翻译：可以通过在衬底的顶部上形成包括第一导电层和第一和第二绝缘层的层状结构来制造接合焊盘结构。通过第一绝缘层和第二绝缘层蚀刻开口，第一绝缘层中的开口宽于第二绝缘层。蚀刻工艺可以分两个步骤进行，第二步骤优先地各向同性蚀刻第一绝缘层，使得第一绝缘层中的开口比第二绝缘层宽，并且第二绝缘层的一部分突出于开口在第一绝缘层之上。然后将金属沉积在开口内并在第二绝缘层的顶部。互连结构形成有导电材料延伸在第二绝缘层的伸出部分的下方。可以在导电材料上形成钝化层。导电材料可以包括阻挡层，塞子和顶部接合焊盘层。

5. 发明授权

US06191602B1 Wafer acceptance testing method and structure of a test key used in the method 有权
标题翻译：晶圆验收测试方法和方法中使用的测试键的结构
公开(公告)号：US06191602B1
公开(公告)日：2001-02-20
申请号：US09220097
申请日：1998-12-23
申请人： Shiang Huang-Lu , Mu-Chun Wang , Kun-Cho Chen
发明人： Shiang Huang-Lu , Mu-Chun Wang , Kun-Cho Chen
IPC分类号： G01R3126
CPC分类号： H01L22/34
摘要： A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.
摘要翻译：提供了具有测试键的晶片验收测试（WAT）方法。测试键结构包括在衬底上的测试结构。层间电介质层覆盖在衬底上以隔离测试结构。接地的金属层位于层间电介质层上。互连结构位于接地的金属层上。导电焊盘层和钝化层依次位于互连结构上。测试结构电耦合到互连结构。互连结构也电耦合到导电焊盘层。接地的金属层没有任何进一步的耦合而接地，使得接地的金属层不耦合到测试结构和互连结构。

6. 发明授权

US06114231A Wafer structure for securing bonding pads on integrated circuit chips and a method for fabricating the same 失效
标题翻译：用于固定集成电路芯片上的焊盘的晶片结构及其制造方法
公开(公告)号：US06114231A
公开(公告)日：2000-09-05
申请号：US691522
申请日：1996-08-02
申请人： Kun-Cho Chen , Jason Jenq
发明人： Kun-Cho Chen , Jason Jenq
IPC分类号： H01L21/768 , H01L23/485 , H01L21/44
CPC分类号： H01L24/02 , H01L21/76804 , H01L21/7684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14
摘要： A wafer structure on an IC chip allows the bonding pads on the IC chip to be firmly secured to the IC chip, thereby preventing detachment of the bonding pads during assembly of the IC package. The wafer structure comprises a substrate on which at least a pad area is defined. The pad area is formed with a first insulating layer, a gate on the first insulating layer, a second insulating layer on the gate, and a third insulating layer on the second insulating layer. The second insulating layer has a plurality of lower openings formed therethrough and the third insulating layer has a plurality of upper openings formed therethrough, each upper opening corresponding to one of the lower openings. The lower openings are wider than the upper openings. Plugs are formed in the lower and upper openings and are bonded to a metallization layer which serves as a bonding pad for the IC chip. The wider lower part of the plugs allows them to be rigidly affixed within the openings, thus allowing the overlaying bonding pad to be firmly secured to the IC chip. Therefore, during assembly of the IC chip, the bonding pad is not readily detached from the IC chip, thus increasing the assembly yield of good IC packages.
摘要翻译： IC芯片上的晶片结构允许IC芯片上的接合焊盘牢固地固定到IC芯片，从而防止在IC封装的组装过程中接合焊盘脱离。晶片结构包括其上限定了至少一个焊盘区域的衬底。焊盘区域形成有第一绝缘层，第一绝缘层上的栅极，栅极上的第二绝缘层和第二绝缘层上的第三绝缘层。第二绝缘层具有穿过其形成的多个下开口，第三绝缘层具有穿过其形成的多个上开口，每个上开口对应于一个下开口。下开口比上开口宽。插头形成在下开口和上开口中，并且与用作IC芯片的焊盘的金属化层接合。插头的较宽的下部允许它们刚性地固定在开口内，从而允许覆盖的焊盘牢固地固定在IC芯片上。因此，在组装IC芯片期间，接合焊盘不容易从IC芯片脱离，因此提高了IC封装的组装成品率。

7. 发明授权

US5937291A Method for forming poly-via connection between load transistor drain and driver transistor gate in SRAM 失效
标题翻译：在SRAM中形成负载晶体管漏极和驱动晶体管栅极之间的多通孔连接的方法
公开(公告)号：US5937291A
公开(公告)日：1999-08-10
申请号：US870202
申请日：1997-06-06
申请人： Meng-Jin Tsai , Kun-Cho Chen
发明人： Meng-Jin Tsai , Kun-Cho Chen
IPC分类号： H01L21/768 , H01L21/8244 , H01L27/11 , H01L21/8234
CPC分类号： H01L27/11 , H01L21/76895 , H01L27/1108 , Y10S438/953
摘要： A manufacturing method applicable for forming a via connection to the thin film transistor in a SRAM unit which resolves the problems arising from a conventional method for forming a via for linking up the drain of a load transistor with the gate of a driver transistor in a SRAM unit by changing the processing sequence and also by forming a plug instead of a via.
摘要翻译：一种适用于在SRAM单元中形成与薄膜晶体管的通孔连接的制造方法，该SRAM单元解决了用于形成用于将负载晶体管的漏极与SRAM中的驱动晶体管的栅极连接的通孔的常规方法所引起的问题通过改变处理顺序并且还通过形成插头而不是通孔来实现。

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